Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- LVDS DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Propagation Delay Diagram
- Output Rise/Fall Time Diagram
- odc & tPeriod Diagram
- VOS Setup Diagram
- VOD Setup Diagram
- IOSD Setup Diagram
- IOS Setup Diagram
- IOFF Setup Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Single Ended Signal Driving Differential Input Diagram
- LVDS Driver Termination
- Clock Input Interface
- CLK/nCLK Input Driven by ICS HiPerClockS LVDS Driver Diagram
- CLK/nCLK Input Driven by 3.3V LVPEC Driver Diagrams
- CLK/nCLK Input Driven by 3.3V LVPEC Driver w/ AC Couple Diagram
- Schematic Example
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
G
ENERAL
D
ESCRIPTION
The ICS8516 is a low skew, high performance
1-to-16 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS. The ICS8516 CLK, nCLK pair can accept
any differential input levels and translates them to 3.3V LVDS
output levels. Utilizing Low Voltage Differential Signaling
(LVDS), the ICS8516 provides a low power, low noise, point-
to-point solution for distributing clock signals over controlled
impedances of 100
.
Dual output enable inputs allow the ICS8516 to be used in a
1-to-16 or 1-to-8 input/output mode.
Guaranteed output and part-to-part skew specifications make
the ICS8516 ideal for those applications demanding well
defined performance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
16 Differential LVDS outputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Maximum output frequency: 700MHz
Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
Translates any single-ended input signal to LVDS
with resistor bias on nCLK input
Multiple output enable inputs for disabling unused
outputs in reduced fanout applications
LVDS compatible
Output skew: 90ps (maximum)
Part-to-part skew: 500ps (maximum)
Propagation delay: 2.4ns (maximum)
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
48-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
OE1
OE2
CLK
nCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
4
8 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
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26
25
V
DD
nQ5
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nQ4
Q4
V
DD
GND
nQ3
Q3
nQ2
Q2
V
DD
V
DD
nQ10
Q10
nQ11
Q11
V
DD
GND
nQ12
Q12
nQ13
Q13
V
DD
nQ14
Q14
nQ15
Q15
GND
CLK
nCLK
GND
Q0
nQ0
Q1
nQ1
ICS8516
Q9
nQ9
Q8
nQ8
GND
OE2
OE1
GND
nQ7
Q7
nQ6
Q6
8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
2
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
T
ABLE
1. P
IN
D
ESCRIPTIONS
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8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
3
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3A. C
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8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
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,
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6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
5
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
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8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
6
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock Outputs
20%
80%
20%
80%
t
R
t
F
V
O D
tsk(o)
nQx
nQ
nQy
Qy
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVDS
3.3V5%
POWER SUPPLY
+
-
Float GND
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
V
DD
tsk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
nCLK
CLK
nQ0:nQ15
Q0:Q15
t
PD
8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
7
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
odc & t
P
ERIOD
V
OS
/
D
VOS
S
ETUP
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ15
Q0:Q15
I
OFF
S
ETUP
I
OSD
S
ETUP
I
OS
S
ETUP
V
OD
/
D
VOD
S
ETUP
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
out
out
LVDS
DC Input
I
OSD
V
DD
out
LVDS
DC Input
I
OS
I
OSB
V
DD
out
LVDS
I
OFF
V
DD
8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
8
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
A
PPLICATION
I
NFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
LVDS D
RIVER
T
ERMINATION
A general LVDS interface is shown in
Figure 2. In a 100
differ-
ential transmission line environment, LVDS drivers require a
matched load termination of 100
across near the receiver in-
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
F
IGURE
2. T
YPICAL
LVDS D
RIVER
T
ERMINATION
3.3V
R1
100
Zo = 50 Ohm
LVDS_Driver
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
3.3V
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VDD
8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
9
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
C
LOCK
I
NPUT
I
NTERFACE
Additional interface examples for the ICS8516 clock input driven
by various types of drives are shown in
Figures 3 to 6. The input
interfaces suggested here are examples only. For example, in
F
IGURE
3. ICS8516 CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
IPER
C
LOCK
S LVDS D
RIVER
F
IGURE
4. ICS8516 CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
F
IGURE
5. ICS8516 CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
6. ICS8516 CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Figure 3, the input termination applies for HiPerClockS LVDS
drivers. If you are using an LVDS driver from another vendor,
use their recommended termination.
3.3V
R1
100
Zo = 50 Ohm
LVDS_Driver
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
3.3V
8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
10
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8516 is: 1821
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
F
IGURE
7. ICS8516 LVDS B
UFFER
S
CHEMATIC
E
XAMPLE
C5
0.1u
(U1-12)
Zo = 50 Ohm
Zo = 50 Ohm
(U1-25)
LVDS_input
+
-
(U1-31)
Zo = 50 Ohm
C3
0.1u
C6
0.1u
U1
8516
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
VD
D
nQ
5
Q5
nQ
4
Q4
VD
D
GND
nQ
3
Q3
nQ
2
Q2
VD
D
nQ1
Q1
nQ0
Q0
GND
nCLK
CLK
GND
Q15
nQ15
Q14
nQ14
VD
D
nQ
10
Q1
0
nQ
11
Q1
1
VD
D
GND
nQ
12
Q1
2
nQ
13
Q1
3
VD
D
Q6
nQ6
Q7
nQ7
GND
OE1
OE2
GND
nQ8
Q8
nQ9
Q9
Zo = 50 Ohm
R16
100
Zo = 50 Ohm
VDD=3.3V
LVDS_input
+
-
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
VDD=3.3V
R10
100
C4
0.1u
C2
0.1u
LVDS_Driver
R17
100
LVDS_input
+
-
(U1-1)
Decoupling capacitors located near the power pins
(U1-6)
(U1-36)
R1
100
C1
0.1u
S
CHEMATIC
E
XAMPLE
Figure 7 shows a schematic example of ICS8516. In this ex-
ample, the input is driven by an LVDS driver. For LVDS buffer, it is
recommended to terminate the unused outputs for better signal
integrity. The decoupling capacitors should be physically located
near the power pin.
8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
11
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
C
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
8
4
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
7
1
.
0
2
2
.
0
7
2
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
5
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
5
.
5
e
C
I
S
A
B
0
5
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
q
0
-
-
7
c
c
c
-
-
-
-
8
0
.
0
Reference Document: JEDEC Publication 95, MS-026
P
ACKAGE
O
UTLINE
- Y S
UFFIX
8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
12
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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8516FY
www.icst.com/products/hiperclocks.html
REV. A MARCH 31, 2003
13
Integrated
Circuit
Systems, Inc.
ICS8516
L
OW
S
KEW
, 1-
TO
-16
D
IFFERENTIAL
-
TO
-LVDS C
LOCK
D
ISTRIBUTION
C
HIP
T
E
E
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