85222AM-02
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
1
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-
TO
-2 LVCMOS / LVTTL-
TO
-
D
IFFERENTIAL
HSTL T
RANSLATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-
to-Differential HSTL translator and a member of
the HiPerClocksTM family of High Performance
Clock Solutions from ICS. The ICS85222-02 has
one single ended clock input. The single ended
clock input accepts LVCMOS or LVTTL input levels and trans-
lates them to HSTL levels. The small outline 8-pin SOIC pack-
age makes this device ideal for applications where space,
high performance and low power are important.
F
EATURES
Two differential HSTL outputs
One LVCMOS/LVTTL clock input
CLK input can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 350MHz
Part-to-part skew: TBD
Propagation delay: 1ns (typical)
V
OH
: 1.4V (maximum)
Full 3.3V operating supply voltage
0C to 70C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free RoHS compliant
packages
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS85222-02
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
Q0
nQ0
CLK
HiPerClockSTM
ICS
V
DD
CLK
nc
GND
8
7
6
5
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
Q1
nQ1
Pullup
85222AM-02
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
2
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-
TO
-2 LVCMOS / LVTTL-
TO
-
D
IFFERENTIAL
HSTL T
RANSLATOR
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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85222AM-02
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
3
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-
TO
-2 LVCMOS / LVTTL-
TO
-
D
IFFERENTIAL
HSTL T
RANSLATOR
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
3C. HSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
112.7C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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85222AM-02
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
4
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-
TO
-2 LVCMOS / LVTTL-
TO
-
D
IFFERENTIAL
HSTL T
RANSLATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
HSTL
Qx
nQx
t
sk(pp)
nQx
Qx
nQy
Qy
PART 1
PART 2
CLK
nQ0, nQ1
Q0, Q1
t
PD
V
DD
2
V
DD
0V
3.3V 5%
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
nQ0, nQ1
Q0, Q1
GND
O
UTPUT
R
ISE
/F
ALL
T
IME
85222AM-02
www.icst.com/products/hiperclocks.html
REV. A JANUARY 25, 2006
5
Integrated
Circuit
Systems, Inc.
ICS85222-02
1-
TO
-2 LVCMOS / LVTTL-
TO
-
D
IFFERENTIAL
HSTL T
RANSLATOR
PRELIMINARY
O
UTPUTS
:
HSTL O
UTPUT
All unused HSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
R
ECOMMENDATIONS
FOR
U
NUSED
O
UTPUT
P
INS
A
PPLICATION
I
NFORMATION
PDF 
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