Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- CLK_EN Timing Diagram
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- LVPECL DC Characteristics
- LVDS DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load Test Circuit Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- odc & tPeriod Diagram
- Differential Input Level Diagram
- Differential Output Level Diagram
- VOS Setup Diagram
- VOD Setup Diagram
- IOSD Setup Diagram
- IOS Setup Diagram
- IOFF Setup Diagram
- IOZ Setup Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Single Ended Signal Driving Differential Input
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
1
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8543 is a low skew, high performance
1-to-4 Differential-to-LVDS clock fanout buffer
and a member of the HiPerClockSTM family of
High Performance Clock Solutions from ICS.
Utilizing Low Voltage Differential Signaling
(LVDS) the ICS8543 provides a low power, low noise, solu-
tion for distributing clock signals over controlled impedances
of 100
. The ICS8543 has two selectable clock inputs. The
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8543 ideal for those applications demanding
well defined performance and repeatability.
F
EATURES
4 differential LVDS outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency: 800MHz
Translates any single ended input signal to LVDS levels
with resistor bias on nCLK input
Output skew: 40ps (maximum)
Part-to-part skew: 500ps (maximum)
Propagation delay: 2.6ns (maximum)
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS8543
20-Lead TSSOP
4.4mm x 6.5mm x 0.92mm body package
G Package
Top View
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
OE
GND
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DD
Q1
nQ1
Q2
nQ2
GND
Q3
nQ3
HiPerClockSTM
,&6
OE
CLK
nCLK
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
D
Q
LE
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
2
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
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8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
3
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
T
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ONTROL
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NPUT
F
UNCTION
T
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Enabled
Disabled
F
IGURE
1 - CLK_EN T
IMING
D
IAGRAM
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
4
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
=0C
TO
70C
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y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
v
i
t
i
s
o
P
5
3
1
.
3
3
.
3
5
6
4
.
3
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
0
5
A
m
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
=0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
E
O
,
L
E
S
_
K
L
C
,
N
E
_
K
L
C
2
5
6
7
.
3
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
E
O
,
L
E
S
_
K
L
C
,
N
E
_
K
L
C
8
.
0
V
I
H
I
t
n
e
r
r
u
C
h
g
i
H
t
u
p
n
I
E
O
,
N
E
_
K
L
C
5
A
L
E
S
_
K
L
C
0
5
1
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
E
O
,
N
E
_
K
L
C
0
5
1
-
A
L
E
S
_
K
L
C
5
-
A
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
=0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
I
H
I
t
n
e
r
r
u
C
h
g
i
H
t
u
p
n
I
K
L
C
V
D
D
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
K
L
C
n
V
D
D
V
=
N
I
V
5
6
4
.
3
=
5
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
K
L
C
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
K
L
C
n
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
V
P
P
e
g
a
t
l
o
V
t
u
p
n
I
k
a
e
P
-
o
t
-
k
a
e
P
5
1
.
0
3
.
1
V
V
R
M
C
2
,
1
E
T
O
N
;
e
g
a
t
l
o
V
t
u
p
n
I
e
d
o
M
n
o
m
m
o
C
5
.
0
V
D
D
5
8
.
0
-
V
V
s
a
d
e
n
i
f
e
d
s
i
e
g
a
t
l
o
v
e
d
o
m
n
o
m
m
o
C
:
1
E
T
O
N
H
I
.
V
s
i
K
L
C
n
,
K
L
C
r
o
f
e
g
a
t
l
o
v
t
u
p
n
i
m
u
m
i
x
a
m
e
h
t
,
s
n
o
i
t
a
c
il
p
p
a
d
e
d
n
e
e
l
g
n
i
s
r
o
F
:
2
E
T
O
N
D
D
.
V
3
.
0
+
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
5
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
=0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
X
A
M
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
0
8
z
H
M
t
D
P
1
E
T
O
N
;
y
a
l
e
D
n
o
i
t
a
g
a
p
o
r
P
f
z
H
M
0
0
8
7
.
1
6
.
2
s
n
t
)
o
(
k
s
4
,
2
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
0
4
s
p
t
)
p
p
(
k
s
4
,
3
E
T
O
N
;
w
e
k
S
t
r
a
P
-
o
t
-
t
r
a
P
0
0
5
s
p
t
R
e
m
i
T
e
s
i
R
t
u
p
t
u
O
z
H
M
0
5
@
%
0
8
o
t
%
0
2
0
5
1
0
5
3
s
p
t
F
e
m
i
T
ll
a
F
t
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H
M
0
5
@
%
0
8
o
t
%
0
2
0
5
1
0
5
3
s
p
c
d
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l
c
y
C
y
t
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D
t
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p
t
u
O
5
4
0
5
5
5
%
.
z
H
M
0
0
5
t
a
d
e
r
u
s
a
e
m
s
r
e
t
e
m
a
r
a
p
ll
A
.
t
n
i
o
p
g
n
i
s
s
o
r
c
t
u
p
t
u
o
l
a
i
t
n
e
r
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f
f
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d
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h
t
o
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t
n
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p
g
n
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s
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o
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c
t
u
p
n
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l
a
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t
n
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r
e
f
f
i
d
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
1
E
T
O
N
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
e
g
a
t
l
o
v
y
l
p
p
u
s
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m
a
s
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h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
2
E
T
O
N
.
s
t
n
i
o
p
s
s
o
r
c
l
a
i
t
n
e
r
e
f
f
i
d
t
u
p
t
u
o
e
h
t
d
e
r
u
s
a
e
M
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
g
n
i
t
a
r
e
p
o
s
e
c
i
v
e
d
t
n
e
r
e
f
f
i
d
n
o
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
3
E
T
O
N
d
e
r
u
s
a
e
m
e
r
a
s
t
u
p
t
u
o
e
h
t
,
e
c
i
v
e
d
h
c
a
e
n
o
s
t
u
p
n
i
f
o
e
p
y
t
e
m
a
s
e
h
t
g
n
i
s
U
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
.
s
t
n
i
o
p
s
s
o
r
c
l
a
i
t
n
e
r
e
f
f
i
d
e
h
t
t
a
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
4
E
T
O
N
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
=0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
I
H
I
t
n
e
r
r
u
C
h
g
i
H
t
u
p
n
I
K
L
C
P
V
D
D
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
K
L
C
P
n
V
D
D
V
=
N
I
V
5
6
4
.
3
=
5
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
K
L
C
P
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
K
L
C
P
n
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
V
P
P
e
g
a
t
l
o
V
t
u
p
n
I
k
a
e
P
-
o
t
-
k
a
e
P
3
.
0
1
V
V
R
M
C
2
,
1
E
T
O
N
;
e
g
a
t
l
o
V
t
u
p
n
I
e
d
o
M
n
o
m
m
o
C
5
.
1
V
D
D
V
V
s
a
d
e
n
i
f
e
d
s
i
e
g
a
t
l
o
v
e
d
o
m
n
o
m
m
o
C
:
1
E
T
O
N
H
I
.
V
s
i
K
L
C
P
n
d
n
a
K
L
C
P
r
o
f
e
g
a
t
l
o
v
t
u
p
n
i
m
u
m
i
x
a
m
e
h
t
,
s
n
o
i
t
a
c
il
p
p
a
d
e
d
n
e
e
l
g
n
i
s
r
o
F
:
2
E
T
O
N
D
D
.
V
3
.
0
+
T
ABLE
4E. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
=0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
O
e
g
a
t
l
o
V
t
u
p
t
u
O
l
a
i
t
n
e
r
e
f
f
i
D
0
0
2
0
8
2
0
6
3
V
m
V
D
O
e
g
n
a
h
C
e
d
u
t
i
n
g
a
M
D
O
V
0
0
4
V
m
V
S
O
e
g
a
t
l
o
V
t
e
s
f
f
O
5
2
1
.
1
5
2
.
1
5
7
3
.
1
V
V
S
O
e
g
n
a
h
C
e
d
u
t
i
n
g
a
M
S
O
V
5
5
2
V
m
I
Z
O
t
n
e
r
r
u
C
e
g
a
k
a
e
L
e
c
n
a
d
e
p
m
I
h
g
i
H
0
1
-
0
1
+
A
I
F
F
O
e
g
a
k
a
e
L
f
f
O
r
e
w
o
P
0
2
-
1
0
2
+
A
I
D
S
O
t
n
e
r
r
u
C
t
i
u
c
r
i
C
t
r
o
h
S
t
u
p
t
u
O
l
a
i
t
n
e
r
e
f
f
i
D
5
.
3
-
5
-
A
m
I
S
O
t
n
e
r
r
u
C
t
i
u
c
r
i
C
t
r
o
h
S
t
u
p
t
u
O
5
.
3
-
5
-
A
m
V
H
O
h
g
i
H
e
g
a
t
l
o
V
t
u
p
t
u
O
4
3
.
1
6
.
1
V
V
L
O
w
o
L
e
g
a
t
l
o
V
t
u
p
t
u
O
9
.
0
6
0
.
1
V
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
6
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
V
DD
GND
SCOPE
Qx
nQx
LVDS
3.3V5% POWER SUPPLY
+
-
Float GND
O
UTPUT
S
KEW
2.1V -0.135V
-1.2V
tsk(o)
nQx
Qx
nQy
Qy
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
7
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
P
ART
-
TO
-P
ART
S
KEW
nQx
Qx
nQy
Qy
PART 1
PART 2
tsk(pp)
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Outputs
20%
80%
80%
20%
t
R
t
F
V
S W I N G
P
ROPAGATION
D
ELAY
t
PD
nCLK, nPCLK
CLK, PCLK
nQ0:nQ3
Q0:Q3
odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ3
Q0:Q3
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
8
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
V
OS
/
D
VOS
S
ETUP
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
D
IFFERENTIAL
O
UTPUT
L
EVEL
V
OS
Cross Points
V
OD
nQx
Qx
V
DD
GND
D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
nCLK, nPCLK
CLK, PCLK
GND
V
DD
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
9
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
V
OD
/
D
VOD
S
ETUP
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
100
I
OSD
S
ETUP
out
out
LVDS
DC Input
I
OSD
V
DD
I
OS
S
ETUP
out
LVDS
DC Input
I
OS
V
DD
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
10
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
I
OZ
S
ETUP
out
out
LVDS
DC Input
3.3V5% POWER SUPPLY
Float GND
+
_
I
OZ
I
OZ
I
OFF
S
ETUP
LVDS
I
OFF
V
DD
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
11
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
F
IGURE
2 - S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
12
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8543 is: 636
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
13
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
14
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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8543BG
www.icst.com/products/hiperclocks.html
REV. C SEPTEMBER 19, 2002
15
Integrated
Circuit
Systems, Inc.
ICS8543
L
OW
S
KEW
, 1-
TO
-4
D
IFFERENTIAL
-
TO
-LVDS F
ANOUT
B
UFFER
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PDF 
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