Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Input Function Table
- CLK_EN Timing Diagram
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVDS DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load Test Circuit Diagram
- Differential Output Level Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- odc & tPeriod Diagram
- VOS Setup Diagram
- VOD Setup Diagram
- IOSD Setup Diagram
- IOS Setup Diagram
- IOZ Setup Diagram
- IOFF Setup Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
1
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8545 is a low skew, high performance
1-to-4 LVCMOS-to-LVDS clock fanout buffer and
a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. Utilizing
Low Voltage Differential Signaling (LVDS) the
ICS8545 provides a low power, low noise, solution for distrib-
uting clock signals over controlled impedances of 100
.
The ICS8545 accepts a LVCMOS input level and translates it
to 3.3V LVDS output levels.
Guaranteed output and part-to-part skew characteristics
make the ICS8545 ideal for those applications demanding well
defined performance and repeatability.
F
EATURES
4 LVDS outputs
2 LVCMOS clock inputs to support redundant
or selectable frequency fanout applications
Maximum output frequency: 650MHz
Translates LVCMOS input signals to LVDS levels
Output skew: 40ps (maximum)
Part-to-part skew: 500ps (maximum)
Propagation delay: 3.6ns (maximum)
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS8545
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm body package
G Package
Top View
GND
CLK_EN
CLK_SEL
CLK1
nc
CLK2
nc
OE
GND
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DD
Q1
nQ1
Q2
nQ2
GND
Q3
nQ3
HiPerClockSTM
,&6
OE
CLK1
CLK2
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
n D
Q
LE
8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
2
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
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8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
3
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
3A. C
ONTROL
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NPUT
F
UNCTION
T
ABLE
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Enabled
Disabled
CLK1, CLK2
CLK_EN
nQ0 - nQ3
Q0 - Q3
F
IGURE
1 - CLK_EN T
IMING
D
IAGRAM
8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
4
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CCx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0C
TO
70C
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,
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8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
5
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
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V
DD
= 3.3V5%, T
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www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
6
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
tsk(o)
nQx
Qx
nQy
Qy
3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
V
DD
GND
SCOPE
Qx
nQx
LVDS
3.3V5% POWER SUPPLY
+
-
Float GND
2.1V -0.135V
-1.2V
V
OS
Cross Points
V
OD
D
IFFERENTIAL
O
UTPUT
L
EVEL
nQ0:nQ3
Q0:Q3
V
DD
GND
8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
7
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Outputs
20%
80%
80%
20%
t
R
t
F
V
S W I N G
P
ROPAGATION
D
ELAY
t
PD
CLK1, CLK2
nQ0:nQ3
Q0:Q3
odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nQ0:nQ3
Q0:Q3
P
ART
-
TO
-P
ART
S
KEW
nQx
Qx
nQy
Qy
PART 1
PART 2
tsk(pp)
8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
8
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
I
OSD
S
ETUP
out
out
LVDS
DC Input
I
OSD
V
DD
V
OD
/
D
VOD
S
ETUP
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
100
V
OS
/
D
VOS
S
ETUP
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
9
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
I
OZ
S
ETUP
I
OFF
S
ETUP
LVDS
I
OFF
V
DD
I
OS
S
ETUP
out
LVDS
DC Input
I
OS
V
DD
out
out
LVDS
DC Input
3.3V5% POWER SUPPLY
Float GND
+
_
I
OZ
I
OZ
8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
10
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8545 is: 644
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
11
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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0
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a
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-
-
0
1
.
0
8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
12
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
T
ABLE
8. O
RDERING
I
NFORMATION
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8545BG
www.icst.com/products/hiperclocks.html
REV. B SEPTEMBER 19, 2002
13
Integrated
Circuit
Systems, Inc.
ICS8545
L
OW
S
KEW
, 1-
TO
-4
LVCMOS-
TO
-LVDS F
ANOUT
B
UFFER
T
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