Integrated
Circuit
Systems, Inc.
8701AY-01
www.icst.com/products/hiperclocks.html
REV. C FEBRUARY 8, 2002
ICS8701-01
L
OW
S
KEW
1,
2
LVCMOS C
LOCK
G
ENERATOR
W
/P
OLARITY
C
ONTROL
1
G
ENERAL
D
ESCRIPTION
The ICS8701-01 is a low skew,
1,
2 LVCMOS
Clock Generator and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The low impedance LVCMOS
outputs are designed to drive 50
series or paral-
lel terminated transmission lines. The effective fanout can be
increased from 20 to 40 by utilizing the ability of the outputs to
drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output frequency
of each bank. The outputs can be utilized in the 1, 2 or a
combination of 1 and 2 modes. The master reset/output en-
able input, nMR/OE, resets the internal dividers and controls
the active and high impedance states of all outputs. The output
polarity inputs, INV0:1, control the polarity (inverting or non-
inverting) of the outputs of each bank. Outputs QA0-QA4 are
inverting for every combination of the INV0:1 input. The timing
relationship between the inverting and non-inverting outputs at
different frequencies is shown in the Timing Diagrams.
The ICS8701-01 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output and part-to-part skew characteristics make the
ICS8701-01 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
F
EATURES
20 LVCMOS outputs, 7
typical output impedance
1 LVCMOS clock input
Maximum output frequency: 250MHz
Selectable inverting and non-inverting outputs
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
Output skew: 300ps (maximum)
Part-to-part skew: 700ps (maximum)
Bank skew: 250ps (maximum)
Multiple frequency skew: 350ps (maximum)
3.3V or mixed 3.3V input, 2.5V output operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
,&6
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
INV0
INV1
QA0 - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
CLK
1
0
1
2
1
0
1
0
1
0
Output
Polarity
Control
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
QC3
V
DDOC
QC4
QD0
V
DDOD
QD1
GND
QD2
GND
QD3
V
DDOD
QD4
QB1
V
DDOB
QB0
QA4
V
DDOA
QA3
GND
QA2
GND
QA1
V
DDOA
QA0
DIV_SELA
DIV_SELB
CLK
GND
V
DD
INV0
GND
INV1
V
DD
nMR/OE
DIV_SELC
DIV_SELD
GND
QB2
GND
QB3
V
DDOB
QB4
QC0
V
DDOC
QC1
GND
QC2
GND
48-Pin LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
ICS8701-01
Integrated
Circuit
Systems, Inc.
8701AY-01
www.icst.com/products/hiperclocks.html
REV. C FEBRUARY 8, 2002
ICS8701-01
L
OW
S
KEW
1,
2
LVCMOS C
LOCK
G
ENERATOR
W
/P
OLARITY
C
ONTROL
3
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
T
ABLE
4A. DC C
HARACTERISTICS
,
V
DD
= V
DDO
X
= 3.3V5%, T
A
= 0C
TO
70C
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3
"
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DDO
X
= 3.3V5%, T
A
= 0C
TO
70C
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