Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- LVCMOS 3.3V DC Characteristics
- 3.3V AC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- LVCMOS 3.3V/2.5V DC Characteristics
- 3.3V/2.5V AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load Test Circuit Diagram
- 3.3V/2.5V Output Load Test Circuit Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- odc & tPeriod Diagram
- Power Considerations
- Driver Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
1
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8701 is a low skew, 1, 2 LVCMOS
C l o c k G e n e r a t o r a n d a m e m b e r o f t h e
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The low impedance LVCMOS
outputs are designed to drive 50
series or
parallel terminated transmission lines. The effective fanout can
be increased from 20 to 40 by utilizing the ability of the out-
puts to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the 1,
2 or a combination of 1 and 2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/
OE, resets the internal frequency dividers and also con-
trols the active and high impedance states of all outputs.
The ICS8701 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output and part-to-part skew characteristics make the
ICS8701 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
F
EATURES
20 LVCMOS outputs, 7
typical output impedance
1 LVCMOS clock input
Maximum output frequency: 250MHz
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
Output skew: 250ps (maximum)
Part-to-part skew: 600ps (maximum)
Bank skew: 200ps (maximum)
Multiple frequency skew: 300ps (maximum)
3.3V or mixed 3.3V input, 2.5V output operating
supply modes
0C to 70C ambient operating temperature
Other divide values available on request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
QA0:QA4
QB0:QB4
QC0:QC4
QD0:QD4
CLK
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
QC3
V
DDO
QC4
QD0
V
DDO
QD1
GND
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GND
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DDO
QD4
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DDO
QB0
QA4
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DDO
QA3
GND
QA2
GND
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DDO
QA0
DIV_SELA
DIV_SELB
CLK
GND
V
DD
BANK_EN0
GND
BANK_EN1
V
DD
nMR/OE
DIV_SELC
DIV_SELD
GND
QB2
GND
QB3
V
DDO
QB4
QC0
V
DDO
QC1
GND
QC2
GND
48-Pin LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
ICS8701
HiPerClockSTM
,&6
1
0
1
2
1
0
1
0
1
0
Bank Enable
Logic
8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
2
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
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8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
3
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. F
UNCTION
T
ABLE
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8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
4
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
=0C
TO
70C
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m
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
=0C
TO
70C
8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
5
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
=0C
TO
70C
l
o
b
m
y
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m
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.
n
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a
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5
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d
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C
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p
s
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h
T
:
7
E
T
O
N
8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
6
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4D. LVCMOS DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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t
e
m
a
r
a
P
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n
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m
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m
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2
=
I
L
O
A
m
7
2
=
5
.
0
V
8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
7
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
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8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
8
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DDO
= +1.25V
1.65V 5%
GND = -1.25V 5%
3.3V/2.5 O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DD,
V
DDO
V
DD
-1.25V 5%
V
DDO
2.05V 5%
GND
1.25V 5%
8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
9
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
O
UTPUT
S
KEW
tsk(o)
Qx
Qy
P
ART
-
TO
-P
ART
S
KEW
Qx
Qy
PART 1
PART 2
tsk(pp)
V
DDO
2
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Outputs
30%
70%
70%
30%
t
R
t
F
V
S W I N G
V
DDO
2
V
DDO
2
V
DDO
2
8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
10
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
P
ROPAGATION
D
ELAY
t
PD
V
DD
2
V
DDO
2
CLK
QAx, QBx, QCx, QDx
odc & t
P
ERIOD
Pulse Width
t
PERIOD
V
DDO
2
QAx, QBx, QCx, QDx
P
OWER
C
ONSIDERATIONS
For Power Dissipation, please refer to a separate Application Note:
Power Dissipation for LVCMOS Buffer.
D
RIVER
T
ERMINATION
For LVCMOS Output Termination, please refer to a separate Application Note:
LVCMOS Driver Termination.
8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
11
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8701 is: 1743
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
12
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
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M
N
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S
N
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D
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L
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C
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L
A
N
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N
8
4
A
-
-
-
-
0
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.
1
1
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5
0
.
0
-
-
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1
.
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2
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3
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4
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4
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1
b
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1
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2
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0
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2
.
0
c
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0
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0
-
-
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2
.
0
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C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
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0
5
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
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S
A
B
0
0
.
7
2
E
.
f
e
R
0
5
.
5
e
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I
S
A
B
0
5
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0
L
5
4
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0
0
6
.
0
5
7
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0
q
0
-
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7
c
c
c
-
-
-
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8
0
.
0
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
13
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
T
ABLE
8. O
RDERING
I
NFORMATION
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
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C
1
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S
C
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C
1
0
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C
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P
F
Q
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4
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0
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C
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S
C
I
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C
1
0
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S
C
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C
0
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8701CY
www.icst.com/products/hiperclocks.html
REV. C AUGUST 19, 2002
14
Integrated
Circuit
Systems, Inc.
ICS8701
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
T
E
E
H
S
Y
R
O
T
S
I
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N
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S
I
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