Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Description
- Pin Characteristics
- Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- LVCMOS 3.3V DC Characteristics
- 3.3V AC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- LVCMOS 3.3V/2.5V DC Characteristics
- 3.3V/2.5V AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load Test Circuit Diagram
- 3.3V/2.5V Output Load Test Circuit Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- odc & tPeriod Diagram
- Power Considerations
- Driver Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
1
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
he ICS8701I is a low skew, 1, 2 Clock Gen-
erator and a member of the HiPerClockSTM family
of High Performance Clock Solutions from ICS.
The low impedance LVCMOS outputs are de-
signed to drive 50
series or parallel terminated
transmission lines. The effective fanout can be increased from
20 to 40 by utilizing the ability of the outputs to drive two se-
ries terminated lines.
The divide select inputs, DIV_SELx, control the output
frequency of each bank. The outputs can be utilized in the 1,
2 or a combination of 1 and 2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/OE,
resets the internal frequency dividers and also controls the
active and high impedance states of all outputs.
The ICS8701I is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output and part-to-part skew characteristics make the
ICS8701I ideal for those clock distribution applications de-
manding well defined performance and repeatability.
F
EATURES
20 LVCMOS outputs, 7
typical output impedance
LVCMOS / LVTTL clock input
Maximum input frequency: 250MHz
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
Bank skew: 200ps
Output skew: 250ps
Multiple frequency skew: 300ps
Part-to-part skew: 600ps
3.3V or mixed 3.3V input, 2.5V output operating supply
-40C to 85C ambient operating temperature
Other divide values available on request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
QA0:QA4
QB0:QB4
QC0:QC4
QD0:QD4
CLK
HiPerClockSTM
,&6
1
0
1
2
1
0
1
0
1
0
Bank Enable
Logic
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
QC3
V
DDO
QC4
QD0
V
DDO
QD1
GND
QD2
GND
QD3
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DDO
QD4
QB1
V
DDO
QB0
QA4
V
DDO
QA3
GND
QA2
GND
QA1
V
DDO
QA0
DIV_SELA
DIV_SELB
CLK
GND
V
DDI
BANK_EN0
GND
BANK_EN1
V
DDI
nMR/OE
DIV_SELC
DIV_SELD
GND
QB2
GND
QB3
V
DDO
QB4
QC0
V
DDO
QC1
GND
QC2
GND
48-Pin LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8701I
8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
2
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
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8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
3
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. F
UNCTION
T
ABLE
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8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
4
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage
4.6V
Inputs
-0.5V to VDD + 0.5V
Outputs
-0.5V to VDDO + 0.5V
Ambient Operating Temperature
-40C to 85C
Storage Temperature
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of product at these condition or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
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8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
5
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
T
ABLE
5A. AC C
HARACTERISTICS
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8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
6
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
T
ABLE
4C. P
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S
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DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
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m
7
2
=
5
.
0
V
8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
7
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
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8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
8
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DDO
= +1.25V
1.65V 5%
GND = -1.25V 5%
3.3V/2.5V O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DD,
V
DDO
V
DD
-1.25V 5%
V
DDO
2.05V 5%
GND
1.25V 5%
8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
9
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
O
UTPUT
S
KEW
tsk(o)
Qx
Qy
P
ART
-
TO
-P
ART
S
KEW
Qx
Qy
PART 1
PART 2
tsk(pp)
V
DDO
2
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Outputs
30%
70%
70%
30%
t
R
t
F
V
S W I N G
V
DDO
2
V
DDO
2
V
DDO
2
8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
10
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
P
ROPAGATION
D
ELAY
t
PD
V
DD
2
V
DDO
2
CLK
QAx, QBx, QCx, QDx
odc & t
P
ERIOD
Pulse Width
t
PERIOD
V
DDO
2
QAx, QBx, QCx, QDx
P
OWER
C
ONSIDERATIONS
For Power Dissipation, please refer to a separate Application Note:
Power Dissipation for LVCMOS Buffer.
D
RIVER
T
ERMINATION
For LVCMOS Output Termination, please refer to a separate Application Note:
LVCMOS Driver Termination.
8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
11
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8701I is: 1743
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8701CYI
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REV. A AUGUST 19, 2002
12
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
N
O
I
T
A
I
R
A
V
C
E
D
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N
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4
A
-
-
-
-
0
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.
1
1
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5
0
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0
-
-
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1
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2
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3
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4
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4
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1
b
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1
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2
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2
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0
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0
-
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0
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C
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S
A
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9
1
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S
A
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.
7
2
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.
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5
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5
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C
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S
A
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0
0
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9
1
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S
A
B
0
0
.
7
2
E
.
f
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R
0
5
.
5
e
C
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S
A
B
0
5
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0
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4
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0
0
6
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0
q
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c
c
c
-
-
-
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8
0
.
0
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
13
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
T
ABLE
7. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support
devices or critical medical instruments.
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-
8701CYI
www.icst.com/products/hiperclocks.html
REV. A AUGUST 19, 2002
14
Integrated
Circuit
Systems, Inc.
ICS8701I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
T
E
E
H
S
Y
R
O
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