IC42S32200

IC42S32200L

Integrated Circuit Solution Inc.

DR036-0D 02/04/2005

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

512K Words x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM

FEATURES

· Concurrent auto precharge
· Clock rate:166/143/125 MHz
· Fully synchronous operation
· Internal pipelined architecture
· Four internal banks (512K x 32bit x 4bank)
· Programmable Mode

-CAS#Latency:2 or 3
-Burst Length:1,2,4,8,or full page
-Burst Type:interleaved or linear burst
-Burst-Read-Single-Write

· Burst stop function
· Individual byte controlled by DQM0-3
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· Single +3.3V ±0.3V power supply
· Interface:LVTTL
· Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin

Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm

· Pb-free package is available.

DESCRIPTION

The ICSI IC42S32200 and IC42S32200L is a high-speed
CMOS configured as a quad 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal,CLK).

Each of the 512K x 32 bit banks is organized as 2048 rows
by 256 columns by 32 bits.Read and write accesses start
at a selected locations in a programmed sequence.
Accesses begin with the registration of a BankActive
command which is then followed by a Read or Write
command

The ICSI IC42S32200 and IC42S32200L provides for
programmable Read or Write burst lengths of 1,2,4,8,or
full page, with a burst termination operation. An auto
precharge function may be enable to provide a self-timed
row precharge that is initiated at the end of the burst
sequence.The refresh functions,either Auto or Self
Refresh are easy to use.

By having a programmable mode register,the system
can choose the most suitable modes to maximize its
performance.

These devices are well suited for applications requiring
high memory bandwidth.

IC42S32200

IC42S32200L

Integrated Circuit Solution Inc.

DR036-0D 02/04/2005

FUNCTIONAL BLOCK DIAGRAM

COLUMN

C O U N T E R

A D D R E S S

B U F F E R

A 0

A 9
B S 0
B S 1

D Q M 0 ~ 3

C L O C K

B U F F E R

COMMAND

D E C O D E R

Sense

Amplifier

Row Decoder

CLK

C K E

C S #
R A S #
C A S #

W E #

D Q 0

D Q 31

Row Decoder

2048 X 256 X 32

CELL ARRAY

(BANK #2)

D Q

B U F F E R

A 1 0 / A P

R E F R E S H
C O U N T E R

M O D E

R E G I S T E R

C O N T R O L

S I G N A L

G E N E R AT O R

C o l u m n D e c o d e r

2 0 4 8 X 2 5 6 X 3 2

C E L L A R R AY

( B A N K # 0 )

2 0 4 8 X 2 5 6 X 3 2

C E L L A R R AY

( B A N K # 1 )

2048 X 256 X 32

CELL ARRAY

(BANK #3)

Row Decoder

C o l u m n D e c o d e r

Sense Amplifier

C o l u m n D e c o d e r

IC42S32200

IC42S32200L

Integrated Circuit Solution Inc.

DR036-0D 02/04/2005

PIN DESCRIPTIONS

Table 1.Pin Details of IC42S32200 and IC42S32200L
Symbol

Type

Description

CLK

Input

Clock:CLK is driven by the system clock.All SDRAM input signals are sampled on the positive edge

of CLK.CLK also increments the internal burst counter and controls the output registers.

CKE

Input

Clock Enable:CKE activates(HIGH)and deactivates(LOW)the CLK signal.If CKE goes low syn-

chronously with clock(set-up and hold time same as other inputs),the internal clock is suspended
from the next clock cycle and the state of output and burst address is frozen as long as the CKE
remains low.When all banks are in the idle state,deactivating the clock controls the entry to the
Power Down and Self Refresh modes.CKE is synchronous except after the device enters Power
Down and Self Refresh modes,where CKE becomes asynchronous until exiting the same mode.
The input buffers,including CLK,are disabled during Power Down and Self Refresh modes,providing
low standby power.

BS0,BS1 Input

Bank Select:BS0 and BS1 defines to which bank the BankActivate,Read,Write,or BankPrecharge

command is being applied.

A0-A10 Input

Address Inputs:A0-A10 are sampled during the BankActivate command (row address A0-A10)and

Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one
location out of the 256K available in the respective bank.During a Precharge command,A10 is
sampled to determine if all banks are to be precharged (A10 =HIGH).

The address inputs also provide the op-code during a Mode Register Set .

CS#

Input

Chip Select:CS#enables (sampled LOW)and disables (sampled HIGH)the command decoder.All

commands are masked when CS#is sampled HIGH.CS#provides for external bank selection on
systems with multiple banks.It is considered part of the command code.

RAS#

Input

Row Address Strobe:The RAS#signal defines the operation commands in conjunction with the

CAS#and WE#signals and is latched at the positive edges of CLK.When RAS# and CS#are as-
serted "LOW"and CAS#is asserted "HIGH,"either the BankActivate command or the Precharge
command is selected by the WE#signal.When the WE#is asserted "HIGH,"the BankActivate com-
mand is selected and the bank designated by BS is turned on to the active state.When the WE#is
asserted "LOW,"the Precharge command is selected and the bank designated by BS is switched to
the idle state after the precharge operation.

CAS#

Input

Column Address Strobe:The CAS#signal defines the operation commands in conjunction with the

RAS#and WE#signals and is latched at the positive edges of CLK. When RAS#is held "HIGH"and
CS#is asserted "LOW,"the column access is started by asserting CAS#"LOW."Then,the Read or
Write command is selected by asserting WE# "LOW"or "HIGH."

WE#

Input

Write Enable:The WE#signal defines the operation commands in conjunction with the RAS#and

CAS#signals and is latched at the positive edges of CLK.The WE#input is used to select the
BankActivate or Precharge command and Read or Write command.

DQM0-3 Input

Data Input/Output Mask:DQM0-DQM3 are byte specific,nonpersistent I/O buffer controls. The I/O

buffers are placed in a high-z state when DQM is sampled HIGH.Input data is masked when DQM
is sampled HIGH during a write cycle.Output data is masked (two-clock latency)when DQM is
sampled HIGH during a read cycle.DQM3 masks DQ31-DQ24,DQM2 masks DQ23-DQ16,DQM1
masks DQ15-DQ8,and DQM0 masks DQ7-DQ0.

DQ0-31 Input/Output

Data I/O:The DQ0-31 input and output data are synchronized with the positive edges of

CLK.The I/Os are byte-maskable during Reads and Writes.

IC42S32200

IC42S32200L

Integrated Circuit Solution Inc.

DR036-0D 02/04/2005

PIN FUNCTION

No Connect:These pins should be left unconnected.

VDDQ

Supply

DQ Power:Provide isolated power to DQs for improved noise immunity.

VSSQ

Supply

DQ Ground:Provide isolated ground to DQs for improved noise immunity.

VDD

Supply

Power Supply:+3.3V ± 0.3V

VSS

Supply

Ground

Pin Assignment (Top View)

VDD
DQ0

VDDQ

DQ1
DQ2

VSSQ

DQ3
DQ4

VDDQ

DQ5
DQ6

VSSQ

DQ7

VDD

DQM 0

/WE

/CAS
/RAS

/CS

BS0
BS1

A10/AP

A 0
A 1
A 2

DQM 2

VDD

DQ16

VSSQ

DQ17
DQ18

VDDQ

DQ19
DQ20

VSSQ

DQ21
DQ22

VDDQ

DQ23

VDD

VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CL K
CKE
A 9
A 8
A 7
A 6
A 5
A 4
A 3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS

1
2
3
4
5
6
7
8
9
1 0
11
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3

8 6
8 5
8 4
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4

PIN CONFIGURATIONS

86-Pin TSOP 2

90-Ball FBGA

1 2 3 4 5 6 7 8 9

(Top View)

Vss

DDQ

SSQ

DDQ

DQM

DDQ

SSQ

DDQ

SSQ

DQM

A10

BA1

CLK

CKE

DQM1

DDQ

SSQ

BA0

RAS

CAS

DQM

SSQ

DDQ

DQ11

DDQ

SSQ

DQ13

DDQ

SSQ

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