Integrated
Circuit
Systems, Inc.
Description
Features
ICS1574B
Block Diagram
User Programmable Laser Engine Pixel Clock Generator
1574B 8/31/00
Supports high resolution laser graphics. PLL/VCO
frequency re-programmable through serial interface
port to 400 MHz; allows less than 1.5ns pixel clock
resolution.
Laser pixel clock output is synchronized with
conditioned beam detect input
Ideal for laser printer, copier and FAX pixel clock
applications
On-chip PLL with internal loop filter
On-chip XTAL oscillator frequency reference
Resettable, programmable counter gives glitch-free
clock alignment
Single 5 volt power supply
Low power CMOS technology
Compact 16-pin 0.150" skinny SOIC package
User re-programmable clock frequency supports
zoom and gray scale functions
The ICS1574B is a very high performance monolithic phase-
locked loop (PLL) frequency synthesizer designed for laser
engine applications. Utilizing ICS's advanced CMOS mixed-
mode technology, the ICS1574B provides a low cost solution
for high-end pixel clock generation for a variety of laser en-
gine product applications.
The pixel clock output (PCLK) frequency is derived from the
main clock by a programmable resettable divider.
Operating frequencies are fully programmable with direct
control provided for reference divider, feedback divider and
post-scaler.
Figure 1
ICS1574B
2
Pin Configuration
16-Pin Skinny SOIC
Pin Descriptions
R
E
B
M
U
N
N
I
P
E
M
A
N
N
I
P
N
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7
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D
PCLKEN
XTAL1
XTAL2
DATCLK
VSS
VSS
PCLK
Reserved
(Do Not Connect)
DATA
HOLD
TEST
VDD
VDDO
Reserved
(Connect to VSS))
(Do Not Connect)
(Do Not Connect)
(Do Not Connect)
Reserved
Reserved
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ICS1574B
3
ICS1574B
PCLK Programmable Divider
The ICS1574B has a programmable divider (referred to in Fig-
ure 1 as the PCLK divider) that is used to generate the PCLK
clock frequency for the pixel clock output. The modulus of
this divider may be set to 3, 4, 5, 6, 8, 10, 12, 16 or 20 under
register control. The design of this divider permits the output
duty factor to be 50/50, even when an odd modulus is se-
lected. The input frequency to this divider is the output of the
PLL post-scaler described below:
The phase of the PCLK output is aligned with the internal
high frequency PLL clock (F
VCO
) immediately after the asser-
tion of the PCLKEN input pulse (active low if PCLKEN_POL
bit is 0 or active high if PCLKEN_POL bit is 1).
When PCLKEN is deasserted, the PCLK output will complete
its current cycle and remain at VDD until the next PCLKEN
pulse. The minimum time PCLKEN must be disabled
(T
PULSE
) is 1/F
PCLK
.
See Figure 2a for an example of PCLKEN enable (negative
polarity) vs. PCLK timing sequences.
Figure 2a
Figure 2b
s
e
u
l
a
V
K
r
e
d
i
v
i
D
K
L
C
P
K
3
2
a
4
5
.
3
b
4
3
5
5
.
4
6
5
.
3
a
8
5
.
5
b
8
5
0
1
7
2
1
5
.
6
a
6
1
5
.
9
b
6
1
9
0
2
2
1
T
K
= K T
VCO
T
d
= LOGIC PROP.DELAY TIME
(typically 9ns with a 10pF load on PCLK)
T
VCO
= 1/F
VCO
The resolution of Ton is one VCO cycle.
The time required for a PCLK cycle start following a PCLKEN
enable is described by Figure 2b and the following table:
Typical values for Tr and Tf with a 10pF load on PCLK are
1ns.
ICS1574B
4
PLL Post-Scaler
A programmable post-scaler may be inserted between the
VCO and the PCLK divider of the ICS1574B. This is useful in
generating lower frequencies, as the VCO has been optimized
for high-frequency operation. The post-scaler is not affected
by the PCLKEN input.
The post-scaler allows the selection of:
VCO frequency
VCO frequency divided by 2
VCO frequency divided by 4
AUX-EN Test Mode
PLL Synthesizer Description --
Ratiometric Mode
The ICS1574B generates its output frequencies using phase-
locked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency pro-
vided to the PLL (see Figure 1). The reference frequency is
generated by an on-chip crystal oscillator or the reference fre-
quency may be applied to the ICS1574B from an external
frequency source.
The phase-frequency detector shown in the block diagram
drives the voltage-controlled oscillator, or VCO, to a fre-
quency that will cause the two inputs to the phase-frequency
detector to be matched in frequency and phase. This occurs
when:
back divider makes use of a dual-modulus prescaler tech-
nique that allows the programmable counters to operate at
low speed without sacrificing resolution. This is an improve-
ment over conventional fixed prescaler architectures that
typically impose a factor-of-four (or larger) penalty in this re-
spect.
Table 1 permits the derivation of "A" & "M" converter pro-
gramming directly from desired modulus.
Digital Inputs
The programming of the ICS1574B is performed serially
by using the DATCLK, DATA, and HOLD pins to load an
internal shift register.
DATA is shifted into the register on the rising edge of
DATCLK. The logic value on the HOLD pin is latched at
the same time. When HOLD is low, the shift register may
be loaded without disturbing the operation of the
ICS1574B. When high, the shift register outputs are trans-
ferred to the control registers, and the new programming
information becomes active. Ordinarily, a high level
should be placed on the HOLD pin when the last data bit is
presented. See Figure 3 for the programming sequence.
The PCLKEN input polarity may be programmed under
register control via Bit 39.
F
(VCO)
:
=
F(XTAL1)
Feedback Divider
Reference Divider
Figure 3
This expression is exact; that is, the accuracy of the output
frequency depends solely on the reference frequency pro-
vided to the part (assuming correctly programmed dividers).
The VCO gain is programmable, permitting the ICS1574B to
be optimized for best performance at all operating frequen-
cies.
The reference divider may be programmed for any modulus
from 1 to 128 in steps of one.
The feedback divider may be programmed for any modulus
from 37 through 392 in steps of one. Any even modulus from
392 through 784 can also be achieved by setting the "double"
bit which doubles the feedback divider modulus. The feed-
Output Description
The PCLK output is a high-current CMOS type drive
whose frequency is controlled by a programmable divider
that may be selected for a modulus of 3, 4, 5, 6, 8, 10, 12,
16 or 20. It may also be suppressed under register control
via Bit 46.
5
ICS1574B
N
I
A
G
O
C
V
Y
C
N
E
U
Q
E
R
F
X
A
M
4
z
H
M
0
0
1
5
z
H
M
0
0
2
6
z
H
M
0
0
3
7
z
H
M
0
0
4
Reference Oscillator
and Crystal Selection
The ICS1574B has circuitry on-board to implement a
Pierce oscillator with the addition of only one external
component, a quartz crystal. Pierce oscillators operate the
crystal in
anti- (also called parallel-) resonant mode. See the AC
Characteristics for the effective capacitive loading to
specify when ordering crystals.
Series-resonant crystals may also be used with the
ICS1574B. Be aware that the oscillation frequency will be
slightly higher than the frequency that is stamped on the
can (typically 0.025 0.05%).
As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend
that the crystal be mounted as closely as possible to the
package. Avoid routing digital signals or the ICS1574B
outputs underneath or near these traces. It is also desirable
to ground the crystal can to the ground plane, if possible.
If an external reference frequency source is to be used with
the ICS1574B, it is important that it be jitter-free. The ris-
ing and falling edges of that signal should be fast and free
of noise for best results.
The loop phase can be locked to either the rising or falling
edges of the XTAL1 input signals, and is controlled by
Bit 56.
Power-On Initialization
The ICS1574B has an internal power-on reset circuit that
performs the following functions:
1) Selects the modulus of the PCLK divider to
be four (4).
2) Sets the multiplexer to pass the reference
frequency to PCLK divider input.
These functions should allow initialization for most appli-
cations that cannot immediately provide for register
programming upon system power-up.
Because the power-on reset circuit is on the VDD supply,
and because that supply is filtered, care must be taken to
allow the reset to de-assert before programming. A safe
guideline is to allow 20 microseconds after the VDD sup-
ply reaches 4 volts.
Programming Notes
VCO Frequency Range: Use the post-divider to keep the
VCO frequency as high as possible within its operating
range.
Divider Range: For best results in normal situations
keep the reference divider modulus as short as possible
(for a frequency at the output of the reference divider in
the few hundred kHz to several MHz range). If you
need to go to a lower phase comparator reference fre-
quency (usually required for increased frequency
accuracy), that is acceptable, but jitter performance will
suffer somewhat.
VCO Gain Programming: Use the minimum gain which
can reliably achieve the VCO frequency desired, as
shown here:
Phase Detector Gain: For most applications and divider
ranges, set P [1, 0] = 10 and set P [2] = 1. Under some
circumstances, setting the P [2] bit "on" can reduce
jitter. During operation at exact multiples of the crystal
frequency, P[2] bit = 0 may provide the best jitter per-
formance.
Board Test Support
It is often desirable to statically control the levels of the
output pins for circuit board test. The ICS1574B supports
this through a register programmable mode, AUX-EN.
When this mode is set, a register bit directly controls the
logic level of the PCLK pin. This mode is activated when
the S[0] and S[1] bits are both set to logic 1. See Register
Mapping for details.
ICS1574B
6
Figure 4
Power Supplies and Decoupling
The ICS1574B has two VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). BOTH of these pins
should connect to the ground plane of the PCB as close to
the package as is possible.
The ICS1574B has a VDDO pin which is the supply of +5
volt power to the output driver. This pin should be con-
nected to the power plane (or bus) using standard
high-frequency decoupling practice. That is, capacitors
should have low series inductance and be mounted close to
the ICS1574B.
The VDD pin is the power supply pin for the PLL synthe-
sizer circuitry and other lower current digital functions.
We recommend that RC decoupling or zener regulation be
provided for this pin (as shown in the recommended appli-
cation circuitry). This will allow the PLL to "track"
through power supply fluctuations without visible effects.
See Figure 4 for typical external circuitry.
7
ICS1574B
]
3
[
K
L
C
P
]
2
[
K
L
C
P
]
1
[
K
L
C
P
]
0
[
K
L
C
P
S
U
L
U
D
O
M
0
0
0
0
3
0
0
0
1
)
a
(
4
0
0
1
0
)
b
(
4
0
0
1
1
5
0
1
0
0
6
0
1
0
1
)
a
(
8
0
1
1
0
)
b
(
8
0
1
1
1
0
1
1
X
0
0
2
1
1
X
0
1
)
a
(
6
1
1
X
1
0
)
b
(
6
1
1
X
1
1
0
2
]
1
[
S
]
0
[
S
N
O
I
T
P
I
R
C
S
E
D
0
0
K
L
C
P
e
h
t
f
o
t
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p
t
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h
T
.
)
L
L
P
(
F
=
)
K
L
C
(
F
.
1
=
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e
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a
c
s
-
t
s
o
P
.
t
u
p
t
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d
0
1
e
h
t
f
o
t
u
p
t
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o
e
h
T
.
2
/
)
L
L
P
(
F
=
)
K
L
C
(
F
.
2
=
r
e
l
a
c
s
-
t
s
o
P
.
t
u
p
t
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o
K
L
C
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h
t
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e
v
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d
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d
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v
i
d
K
L
C
P
1
0
e
h
t
f
o
t
u
p
t
u
o
e
h
T
.
4
/
)
L
L
P
(
F
=
)
K
L
C
(
F
.
4
=
r
e
l
a
c
s
-
t
s
o
P
.
t
u
p
t
u
o
K
L
C
P
e
h
t
s
e
v
i
r
d
r
e
d
i
v
i
d
K
L
C
P
1
1
L
C
P
_
X
U
A
e
h
T
.
E
D
O
M
T
S
E
T
N
E
-
X
U
A
K
e
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b
.
t
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p
t
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K
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C
P
Register Mapping -- ICS1574B
NOTE:
It is not necessary to understand the function of these bits to use the ICS1574B. PC Software is available from ICS to
automatically generate all register values based on requirements. Contact factory for details.
BIT(S)
BIT REF.
DESCRIPTION
1 4
PCLK[0]..PCLK[3]
Sets PCLK divider modulus according to this table.
These bits are set to implement a divide-by-four on power-up.
(X =
Don't Care
)
5, 6
Reserved
Must be set to 0.
7
Reserved
Must be set to 1.
8
SELXTAL
Normally set to 0. When set to logic 1, passes the reference
frequency to the post-scaler instead of the PLL output
(defaults to 1 on power-up).
9
Reserved
Must be set to 0.
10
Reserved
Must be set to 1.
11, 12
Reserved
Must be set to 0.
13 14
S[0]..S[1]
PLL post-scaler / test mode select bits.
ICS1574B
8
]
1
[
P
]
0
[
P
N
I
A
G
)
n
a
i
d
a
r
/
A
(
0
0
5
0
.
0
0
1
5
1
.
0
1
0
5
.
0
1
1
5
.
1
]
2
[
V
]
1
[
V
]
0
[
V
N
I
A
G
O
C
V
)
t
l
o
V
/
z
H
M
(
1
0
0
0
3
1
0
1
5
4
1
1
0
0
6
1
1
1
0
8
BIT(S)
BIT REF.
DESCRIPTION
15
Reserved
Must be set to 0.
16
AUX_PCLK
Must be set to 0 except when in the AUX-EN test mode.
When in the AUX-EN test mode, this bit controls the
PCLK output.
17 24
Reserved
Must be set to 0.
25 27
V[0]..V[2]
Sets the gain of VCO
28
Reserved
Must be set to 1.
29 30
P[0]..P[1]
Sets the gain of the phase detector according to this table:
31
Reserved
Must be set to 0.
32
P[2]
Phase detector tuning bit. Should normally be set to one.
See text.
33 38
M[0]..M[5]
M counter control bits. Modulus = value + 1.
39
PCLKEN_POL
When = 0, PCLK output enabled when PCLKEN input is
low. When = 1, PCLK output enabled when PCLKEN input
is high.
40
DBLFREQ
Doubles modulus of dual-modulus prescaler (from 6 / 7 to
12 /14).
41 44
A[0]..A[3]
Controls A counter. When set to zero, modulus = 7.
Otherwise, modulus = 7 for "value" underflows of the
prescaler, and modulus = 6 thereafter until M counter
underflows.
9
ICS1574B
BIT(S)
BIT REF.
DESCRIPTION
45
Reserved
Must be set to 1.
46
PCLK_EN
Must be set to 0.
Disables the PCLK divider when set to 1 regardless of
PCLKEN input state.
47, 48
Reserved
Must be set to 0.
49 55
R[0]..R[6]
Reference divider modulus control bits.
Modulus = value +1.
56
REF_POL
PLL locks to rising edge of XTAL1 input when
REFPOL = 1, falling edge of XTAL1 when REFPOL = 0.
ICS1574B
10
Table 1 -- "A" & "M" Divider Programming
Feedback Divider Modulus Table
Notes:
To use this table, find the desired modulus in the table. Follow the column up to find the A divider programming values. Follow the
row to the left to find the M divider programming. Some feedback divisors can be achieved with two or three combinations of divider settings.
Any are acceptable for use.
The formula for the effective feedback modulus is:
N =[(M +1) 6] +A
except when A=0, then:
N=(M +1) 7
Under all circumstances:
A
M
-
]
0
[
A
.
.
]
2
[
A
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
-
]
0
[
A
.
.
]
2
[
A
1
0
0
0
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
]
0
[
M
.
.
]
5
[
M
]
0
[
M
.
.
]
5
[
M
0
0
0
0
0
0
7
0
0
0
0
0
1
9
9
1
0
0
2
1
0
2
2
0
2
3
0
2
4
0
2
5
0
2
1
3
2
1
0
0
0
0
0
3
1
4
1
1
0
0
0
0
1
5
0
2
6
0
2
7
0
2
8
0
2
9
0
2
0
1
2
1
1
2
8
3
2
0
1
0
0
0
0
9
1
0
2
1
2
0
1
0
0
0
1
1
1
2
2
1
2
3
1
2
4
1
2
5
1
2
6
1
2
7
1
2
5
4
2
1
1
0
0
0
0
5
2
6
2
7
2
8
2
1
1
0
0
0
1
7
1
2
8
1
2
9
1
2
0
2
2
1
2
2
2
2
2
3
2
2
2
5
2
0
0
1
0
0
0
1
3
2
3
3
3
4
3
5
3
0
0
1
0
0
1
3
2
2
4
2
2
5
2
2
6
2
2
7
2
2
8
2
2
9
2
2
9
5
2
1
0
1
0
0
0
7
3
8
3
9
3
0
4
1
4
2
4
1
0
1
0
0
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4
11
ICS1574B
Absolute Maximum Ratings
VDD, VDDO (measured to V
SS
) . . . . . . . . 7.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . V
SS
0.5 V to V
DD
+0.5 V
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . V
SS
0.5 V to V
DD O
+0.5 V
Ambient Operating Temperature . . . . . . . 55 C to +125 C
Storage Temperature . . . . . . . . . . . . . . . . . 65 C to +150 C
Junction Temperature . . . . . . . . . . . . . . . . . 175 C
Soldering Temperature . . . . . . . . . . . . . . . . 260 C
DC Electrical Characteristics
TTL-Compatible Inputs
(DATCLK, DATA, HOLD, PCLKEN)
Recommended Operating Conditions
VDD, VDDO (measured to V
SS
) . . . . . . . . 4.75 to 5.25 V
Operating Temperature (Ambient) . . . . . . 0 to +70C
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ICS1574B
12
Ordering Information
ICS1574BM / ICS1574BEB
16-Pin Skinny SOIC Package
AC Electrical Characteristics
ICS 1574B M
Package Type
M = SOIC EB = Evaluation Board
Device Type
Prefix
ICS, AV = Standard Device GSP = Genlock Device
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