ICS181-03
Low EMI Clock Generator
MDS 181-03 A
1
Revision 110404
I n t e gra t e d C i r c u i t S y s t e m s
l
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
l
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
l
w w w. i c s t . c o m
Description
The ICS181-03 generates a low EMI output clock from
a clock or crystal input. The device uses ICS'
proprietary mix of analog and digital Phase-Locked
Loop (PLL) technology to spread the frequency
spectrum of the output, thereby reducing the frequency
amplitude peaks by several dB.
The ICS181-03 offers down spread selection of -1.25%
and -3.75%. Refer to the MK1714-01/02 for the widest
selection of input frequencies and multipliers.
ICS offers a complete line of EMI reducing clock
generators. Consult us when you need to remove
crystals and oscillators from your board.
Features
Pin and function compatible to Cypress W181-03
Packaged in 8-pin SOIC
Provides a spread spectrum output clock
Accepts a clock input and provides same frequency
dithered output
Input frequency of 46 to 75 MHz for Clock input
Peak reduction by 7dB - 14dB typical on 3rd - 19th
odd harmonics
Spread percentage selection for -1.25% and -3.75%
Operating voltage of 3.3 V and 5 V
Advanced, low-power CMOS process
Block Diagram
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
SS%
CLK
GND
VDD
SSON#
CLK
Clock Buffer
FS1
L
OW
EMI C
LOCK
G
ENERATOR
ICS181-03
MDS 181-03 A
2
Revision 110404
I n t e gra t e d C i r c u i t S y s t e m s
l
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
l
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
l
w w w. i c s t . c o m
Pin Assignment
Spread Spectrum Select Table
0 = connect to GND
1 = connect directly to VDD
Note: SS% pin has an internal pull-up resistor
Frequency Range Selection Table
Pin Descriptions
1
2
3
CLKIN
4
NC
GND
FS1
SS%
VDD
CLKOUT
8
7
6
5
SSON#
8-pin (150 mil) SOIC
SS%
(Pin 4)
Spread
Direction
Spread
Percentage (%)
0
Down
-1.25%
1
Down
-3.75%
FS1
(Pin 7)
Frequency Range Selection
(MHz)
0
46-60
1
58-75
Pin
Number
Pin
Name
Pin Type
Pin Description
1
CLKIN
Input
Clock Input.
2
NC
--
No connect. Do not connect this pin to anything.
3
GND
Power
Connect to ground.
4
SS%
Input
Select pin for spread amount. See table above. Internal pull-up resistor.
5
CLKOUT
Output
Spread spectrum clock output per table above.
6
VDD
Power
Connect to 3.3 V or 5 V.
7
FS1
Input
Select pin for input frequency. See table above. Internal pull-up resistor.
8
SSON#
Input
Spread Spectrum Control. This pin enables spread spectrum when low.
Internal pull-down resistor.
L
OW
EMI C
LOCK
G
ENERATOR
ICS181-03
MDS 181-03 A
3
Revision 110404
I n t e gra t e d C i r c u i t S y s t e m s
l
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
l
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
l
w w w. i c s t . c o m
External Components
The ICS181-03 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD and GND on pins 6 and 3, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50
trace (a commonly used
trace impedance) place a 33
resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
value of these capacitors is given by the following
equation:
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI, the 33
series termination resistor
(if needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS181-03. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS181-03. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70
C
Storage Temperature
-65 to +150
C
Junction Temperature
125
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.135
+5.5
V
L
OW
EMI C
LOCK
G
ENERATOR
ICS181-03
MDS 181-03 A
4
Revision 110404
I n t e gra t e d C i r c u i t S y s t e m s
l
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
l
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
l
w w w. i c s t . c o m
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V
5%, Ambient Temperature 0 to +70
C
Unless stated otherwise, VDD = 5 V,
10%, Ambient Temperature 0 to +70
C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.135
3.465
V
Supply Current
IDD
No load, at 3.3 V
18
32
mA
Input High Voltage
V
IH
2.4
V
Input Low Voltage
V
IL
0.8
V
Output High Voltage
V
OH
I
OH
= -4 mA
VDD-0.4
V
Output High Voltage
V
OH
I
OH
= -15 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 15 mA
0.4
V
Input Capacitance
C
IN
All pins except CLKIN
5
7
pF
CLKIN pin only
6
10
pF
Output Impedance
Rout
25
ohms
Input Pull-up Resistor
500
K
Power-up Time
First locked clock
cycle after steady
power
5
ms
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
4.5
5
5.5
V
Supply Current
IDD
No load, at 3.3 V
30
50
mA
Input High Voltage
V
IH
0.7VDD
V
Input Low Voltage
V
IL
0.15VDD
V
Output High Voltage
V
OH
I
OH
= -24 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 24 mA
0.4
V
Output Impedance
Rout
20
ohms
Input Capacitance
C
IN
All pins except CLKIN
5
7
pF
CLKIN pin only
6
10
pF
Input Pull-up Resistor
500
K
Power-up Time
First locked clock
cycle after steady
power
5
ms
L
OW
EMI C
LOCK
G
ENERATOR
ICS181-03
MDS 181-03 A
5
Revision 110404
I n t e gra t e d C i r c u i t S y s t e m s
l
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
l
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
l
w w w. i c s t . c o m
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V5% or 5 V10%, Ambient Temperature 0 to +70
C, C
L
=15 pf
Note 1: Measured with 15 pF load
Thermal Characteristics
Marking Diagram
Marking Diagram (Pb free)
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week
that the part was assembled.
3. "LF" denotes Pb (lead) free package.
4. Bottom marking: country of origin.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input/Output Clock Frequency
46
75
MHz
Input Clock Duty Cycle
Time above VDD/2
40
60
%
Output Clock Duty Cycle
Note 1
40
50
60
%
Output Rise Time
t
OR
0.8 to 2.4 V, note 1
2
5
ns
Output Fall Time
t
OF
2.4 to 0.8 V, note 1
2
5
ns
Jitter
Cycle-to-cycle
250
300
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
150
C/W
JA
1 m/s air flow
140
C/W
JA
3 m/s air flow
120
C/W
Thermal Resistance Junction to Case
JC
40
C/W
181M-03
######
YYWW
1
4
5
8
181M03LF
######
YYWW
1
4
5
8
L
OW
EMI C
LOCK
G
ENERATOR
ICS181-03
MDS 181-03 A
6
Revision 110404
I n t e gra t e d C i r c u i t S y s t e m s
l
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
l
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
l
w w w. i c s t . c o m
Package Outline and Package Dimensions
(8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
"LF" denotes Pb free packaging.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking
Shipping
packaging
Package
Temperature
ICS181M-03
see page 5
Tubes
8-pin SOIC
0 to +70
C
ICS181M-03T
Tape and Reel
8-pin SOIC
0 to +70
C
ICS181M-03LF
Tubes
8-pin SOIC
0 to +70
C
ICS181M-03LFT
Tape and Reel
8-pin SOIC
0 to +70
C
INDEX
AREA
1 2
8
D
E
SEATING
PLANE
A1
A
e
- C -
B
.10 (.004)
C
C
L
H
h x 45
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
1.35
1.75
.0532
.0688
A1
0.10
0.25
.0040
.0098
B
0.33
0.51
.013
.020
C
0.19
0.25
.0075
.0098
D
4.80
5.00
.1890
.1968
E
3.80
4.00
.1497
.1574
e
1.27 BASIC
0.050 BASIC
H
5.80
6.20
.2284
.2440
h
0.25
0.50
.010
.020
L
0.40
1.27
.016
.050
0
8
0
8
PDF 
ZIP