ICS276
MDS 276 A
1
Revision 040805
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
Triple PLL Field Programmable VCXO Clock Synthesizer
PRELIMINARY INFORMATION
Description
The ICS276 field programmable VCXO clock
synthesizer generates up to three high-quality,
high-frequency clock outputs including multiple
reference clocks from a low-frequency crystal input. It
is designed to replace crystals and crystal oscillators in
most electronic systems.
Using ICS' VersaClock
TM
software to configure PLLs
and outputs, the ICS276 contains a One-Time
Programmable (OTP) ROM for field programmability.
Programming features include VCXO and eight
selectable configuration registers.
Each of the outputs are powered by a single VDDO
voltage. VDDO may vary from 1.8 V to VDD.
Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace VCXOs,
multiple crystals and oscillators, saving board space
and cost.
The ICS276 is also available in factory programmed
custom versions for high-volume applications.
Features
Packaged as 16-pin TSSOP
Eight addressable registers
Replaces multiple crystals and oscillators
Output frequencies up to 200 MHz at 3.3 V
Input crystal frequency of 5 to 27 MHz
Up to three reference outputs
Operating voltages of 3.3 V
VDDO output control from 1.8 V to 3.3 V
Controllable output drive levels
Advanced, low-power CMOS process
Available in Pb (lead) free packaging
Block Diagram
Voltage
Controlled
Crystal
Oscillator
GND
2
3
VDD
PDTS
PLL2
PLL3
Divide
Logic
and
Output
Enable
Control
S2:S0
CLK1
CLK3
CLK2
3
OTP
ROM
with
PLL
Values
X2
Crystal
External capacitors
are required.
X1
PLL1
VIN
VDDO
Triple PLL Field Programmable VCXO Clock Synthesizer
MDS 276 A
2
Revision 040805
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS276
PRELIMINARY INFORMATION
Pin Assignment
Pin Descriptions
12
1
11
2
10
3
9
4
S0
5
S1
6
VDD
7
VIN
8
VDD
PDTS
S2
GND
GND
VDD
VDDO
CLK1
CLK3
16
15
14
13
CLK2
X2
16 pin (173 mil) TSSOP
X1/ICLK
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
VIN
Input
Voltage input to VCXO. Zero to 3.3 V signal which controls the VCXO
frequency
2
S0
Input
Select pin 0. Internal pull-up resistor.
3
S1
Input
Select pin 1. Internal pull-up resistor.
4
VDD
Power
Connect to +3.3 V.
5
VDDO
Power
Power supply for outputs.
6
CLK1
Output
Output clock 1. Weak internal pull-down when tri-state.
7
GND
Power
Connect to ground.
8
X1
XI
Crystal input. Connect this pin to a crystal.
9
X2
XO
Crystal Output. Connect this pin to a crystal.
10
VDD
Power
Connect to +3.3 V.
11
CLK2
Output
Output clock 2. Weak internal pull-down when tri-state.
12
CLK3
Output
Output clock 3. Weak internal pull-down when tri-state.
13
GND
Power
Connect to ground.
14
PDTS
Input
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
15
VDD
Power
Connect to +3.3 V.
16
S2
Input
Select pin 2. Internal pull-up resistor.
Triple PLL Field Programmable VCXO Clock Synthesizer
MDS 276 A
3
Revision 040805
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS276
PRELIMINARY INFORMATION
External Components
The ICS276 requires a minimum number of external
components for proper operation.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS276 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias on the decoupling circuit.
Quartz Crystal
The ICS276 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section shown must be followed.
The frequency of oscillation of a quartz crystal is
determined by its "cut" and by the load capacitors
connected to it. The ICS276 incorporates on-chip
variable load capacitors that "pull" (change) the
frequency of the crystal. The crystal specified for use
with the ICS276 is designed to have zero frequency
error when the total of on-chip + stray capacitance is 14
pF.
Recommended Crystal Parameters:
Initial Accuracy at 25
C
20 ppm
Temperature Stability
30 ppm
Aging
20 ppm
Load Capacitance
14 pf
Shunt Capacitance, C0
7 pF Max
C0/C1 Ratio
250 Max
Equivalent Series Resistance
35
Max
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS276. There should be no via's between
the crystal pins and the X1 and X2 device pins. There
should be no signal traces underneath or close to the
crystal. See application note MAN05.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the ICS276 to 3.3 V. Connect pin 1
of the ICS276 to the second power supply. Adjust the
voltage on pin 1 to 0V. Measure and record the
frequency of the CLK output.
2. Adjust the voltage on pin 1 to 3.3 V. Measure and
record the frequency of the same output.
To calculate the centering error:
Where:
f
target
= nominal crystal frequency
Error
10
6
x
f
3.0V
f
t
et
arg
(
) f
0V
f
t
et
arg
(
)
+
f
t
et
arg
-----------------------------------------------------------------------
error
xtal
=
Triple PLL Field Programmable VCXO Clock Synthesizer
MDS 276 A
4
Revision 040805
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS276
PRELIMINARY INFORMATION
error
xtal
=actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than 25 ppm, no
adjustment is needed. If the centering error is more
than 25 ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS for details.) If the centering
error is more than 25 ppm positive, add identical fixed
centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by:
External Capacitor = 2 x (centering error)/(trim
sensitivity)
Trim sensitivity is a parameter which can be supplied by
your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than 25 ppm).
ICS276 Configuration Capabilities
The architecture of the ICS276 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 1024 and N = 1 to
32,895.
The ICS276 also provides separate output divide
values, from 2 through 63, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
Output Drive Control
The ICS271 has two output drive settings. For
VDDO=VDD, low drive should be selected when
outputs are less than 100 MHz. High drive should be
selected when outputs are greater than 100 MHz.
For VDDO<2.8V, high drive should be selected for all
output frequencies.
(Consult the AC Electrical Characteristics for output
rise and fall times for each drive option.)
ICS VersaClock Software
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user's target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS276. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
OutputFreq
REFFreq
M
N
-----
=
Parameter
Condition
Min.
Typ.
Max.
Units
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+0.5
V
Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Triple PLL Field Programmable VCXO Clock Synthesizer
MDS 276 A
5
Revision 040805
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS276
PRELIMINARY INFORMATION
Recommended Operation Conditions
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85
C
Storage Temperature
-65
150
C
Soldering Temperature
Max 10 seconds
260
C
Junction Temperature
125
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature (ICS276PG/PGLF)
0
+70
C
Ambient Operating Temperature (ICS276PGI/PGILF)
-40
+85
C
Power Supply Voltage (measured in respect to GND)
+3.135
+3.3
+3.465
V
Power Supply Ramp Time
4
ms
Reference crystal parameters
Refer to page 3
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.135
3.465
V
VDDO Voltage
1.80
VDD
V
Operating Supply Current
Input High Voltage
IDD
Config. Dependent - See
VersaClock
TM
Estimates
mA
Three 33.3333 MHz outs,
VDD=VDDO=3.3 V;
PDTS = 1, no load, Note 1
20
mA
PDTS = 0, no load, Note 1
500
A
Input High Voltage
V
IH
S2:S0
VDD/2+1
V
Input Low Voltage
V
IL
S2:S0
0.4
V
Input High Voltage, PDTS
V
IH
VDD-0.5
V
Input Low Voltage, PDTS
V
IL
0.4
V
Input High Voltage
V
IH
ICLK
VDD/2+1
V
Input Low Voltage
V
IL
ICLK
VDD/2-1
V
Output High Voltage
(CMOS High)
V
OH
I
OH
= -4 mA
VDD-0.4
V
Output High Voltage
V
OH
I
OH
= -8 mA (Low Drive);
I
OH
= -12 mA (High Drive)
2.4
VDDO-0.4
V
Output Low Voltage
V
OL
I
OL
= 8 mA (Low Drive);
I
OL
= 12 mA (High Drive)
0.4
V
Short Circuit Current
I
OS
Low Drive
40
mA
High Drive
70
Nom. Output Impedance
Z
O
20
Parameter
Condition
Min.
Typ.
Max.
Units
Triple PLL Field Programmable VCXO Clock Synthesizer
MDS 276 A
6
Revision 040805
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS276
PRELIMINARY INFORMATION
Note 1: Example with 25 MHz crystal input, three unloaded 33.3 MHz outputs and VDD = VDDO = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85
C
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Note 2: Measured with 15 pF load.
Note 3: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%.
Internal pull-up resistor
R
PUS
S2:S0, PDTS
190
k
Internal pull-down
resistor
R
PD
CLK outputs
120
k
Input Capacitance
C
IN
Inputs
4
pF
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
F
IN
Fundamental crystal
5
27
MHz
Output Frequency
VDDO=VDD
0.314
200
MHz
1.8 V<VDDO<2.8
0.314
150
MHz
Crystal Pullability
F
P
0V< VIN < 3.3 V, Note 1,
Config. Dependent
100
ppm
VCXO Gain
VIN = VDD/2 + 1 V,
Note 1, Config.
Dependent
120
ppm/V
Output Rise/Fall Time
t
OF
80% to 20%, high drive,
Note 2
1.0
ns
Output Rise/Fall Time
t
OF
80% to 20%, low drive,
Note 2
2.0
ns
Duty Cycle
Note 3
40
49-51
60
%
Power-up Time
PLL lock-time from
power-up
4
10
ms
PDTS goes high until
stable CLK output
0.6
2
ms
One Sigma Clock Period Jitter
Configuration Dependent
50
ps
Maximum Absolute Jitter
t
ja
Deviation from Mean.
Configuration Dependent
+200
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Triple PLL Field Programmable VCXO Clock Synthesizer
MDS 276 A
7
Revision 040805
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS276
PRELIMINARY INFORMATION
Thermal Characteristics
Marking Diagrams
Marking Diagrams (Pb free)
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. "I" denotes industrial temperature range (if applicable).
4. "L" denotes Pb (lead) free package.
5. Bottom marking: country of origin.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
78
C/W
JA
1 m/s air flow
70
C/W
JA
3 m/s air flow
68
C/W
Thermal Resistance Junction to Case
JC
37
C/W
1
8
9
16
276PG
######
YYWW
1
8
9
16
276PGI
######
YYWW
1
8
9
16
276PGL
######
YYWW
1
8
9
16
276PGIL
######
YYWW
Triple PLL Field Programmable VCXO Clock Synthesizer
MDS 276 A
8
Revision 040805
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS276
PRELIMINARY INFORMATION
Package Outline and Package Dimensions
(16-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
VersaClock
TM
is a trademark of Integrated Circuit Systems, Inc. All rights reserved.
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS276PG
See page 7
Tubes
16-pin TSSOP
0 to +70
C
ICS276PGI
Tubes
16-pin TSSOP
-40 to +85
C
ICS276PGLF
Tubes
16-pin TSSOP
0 to +70
C
ICS276PGILF
Tubes
16-pin TSSOP
-40 to +85
C
INDEX
AREA
1 2
24
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
.10 (.004)
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.10
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
.018
.030
0
8
0
8
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