Document Outline
- General Description
- Features
- Frequency Select Function Table
- Pin Assignment
- Block Diagram
- Pin Description
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply 2.5V DC Characteristics
- LVCMOS DC Characteristics
- LVDS DC Characteristics
- Crystal Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise Plot
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input and Output Pins
- 2.5V LVDS Driver Termination
- Power Considerations
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
1
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
T h e I C S 8 4 4 0 0 2 I - 0 1 i s a 2 o u t p u t LV D S
Synthesizer optimized to generate Ethernet
reference clock frequencies and is a mem-
b e r o f t h e H i Pe r C l o ck s
T M
fa m i l y o f h i g h
performance clock solutions from ICS. Using a
25MHz, 18pF parallel resonant crystal, the following
frequencies can be generated based on the 2 frequency
select pins (F_SEL[1:0]): 156.25MHz, 125MHz and
62.5MHz. The ICS844002I-01 uses ICS' 3
rd
generation
low phase noise VCO technology and can achieve <1ps
typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844002I-01 is packaged in a small
20-pin TSSOP package.
F
EATURES
Two LVDS outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 156.25MHz,
125MHz, 62.5MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical)
Full 2.5V supply mode
-40C to 85C ambient operating temperature
Available in both, standard and RoHS/Lead-Free compliant
packages
HiPerClockSTM
ICS
1
1
0
1
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
M = 25 (fixed)
F_SEL[1:0]
0 0 4
0 1 5
1 0 10
1 1 not used
2
OSC
B
LOCK
D
IAGRAM
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
F_SEL[1:0]
nPLL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
nXTAL_SEL
MR
Q0
nQ0
Q1
nQ1
Pulldown
Pulldown
25MHz
Pulldown
Pulldown
Pulldown
ICS844002I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
nc
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
1
2
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10
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19
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17
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11
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DDO
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GND
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DD
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REF_CLK
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XTAL_OUT
F_SEL1
P
IN
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844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
2
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
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844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
3
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
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ABLE
3C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
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844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
4
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
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5. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
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844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
5
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
156.25MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
156.25MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.41ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
1k
10k
100k
1M
10M
100M
dBc
Hz
N
OISE
P
OWER
Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
Ethernet Filter to raw data
844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
6
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
RMS P
HASE
J
ITTER
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
t
sk(o)
Qy
Qx
nQy
nQx
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
O
FFSET
V
OLTAGE
S
ETUP
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0, Q1
nQ0, nQ1
P
ROPAGATION
D
ELAY
O
UTPUT
S
KEW
SCOPE
Qx
nQx
LVDS
2.5V5%
POWER SUPPLY
+
Float GND
V
DD,
V
DDO
V
DDA
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
D
IFFERENTIAL
O
UTPUT
V
OLTAGE
S
ETUP
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
7
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS844002I-01 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 25MHz, 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error.
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844002I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
2.5V
.01
F
V
DD
C1
22p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
8
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
REF_CLK I
NPUT
:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the REF_CLK to
ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100
across. If they are left floating, we
recommend that there is no trace attached.
transmission line environment. For buffer with multiple LDVS
driver, it is recommended to terminate the unused outputs.
2.5V LVDS D
RIVER
T
ERMINATION
Figure 3
shows a typical termination for LVDS driver in
characteristic impedance of 100
differential (50 single)
F
IGURE
3. T
YPICAL
LVDS D
RIVER
T
ERMINATION
2.5V
100 Ohm Differential Transmission Line
2.5V
LVDS_Driv er
R1
100
+
-
100
Differential Transmission Line
844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
9
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844002I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844002I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 2.5V + 5% = 2.625V, which gives worst case results.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 2.625V * 85mA = 223mW
Power (outputs)
MAX
= V
DDO_MAX
* I
DDO_MAX
= 2.625V * 70mA = 184mW
Total Power
_MAX
= 223mW + 184mW = 407mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
q
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming
a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.407W * 66.6C/W = 112C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
20-P
IN
TSSOP, F
ORCED
C
ONVECTION
JA
by Velocity (Meters per Second)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
10
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS844002I-01 is: 2914
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
11
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
N
I
M
X
A
M
N
0
2
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
4
.
6
0
6
.
6
E
C
I
S
A
B
0
4
.
6
1
E
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3
.
4
0
5
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4
e
C
I
S
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0
5
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0
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a
a
a
-
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0
1
.
0
Reference Document: JEDEC Publication 95, MO-153
844002AGI-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 5, 2006
12
Integrated
Circuit
Systems, Inc.
ICS844002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and F
EMTO
C
LOCKS
are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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