Document Outline
- General Description
- Features
- Control Input Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Common Configuration Table
- Programmable M Output Divider Function Table
- Programmable N Output Divider Function Table
- Bypass Mode Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 2.5V DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- Input Frequency Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise Plot
- Parameter Measurement Information
- Parameter Measurement Information continued
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input and Output Pins
- Termination for 3.3V LVPECL Output
- Termination for 2.5V LVPECL Output
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Ciruit and Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
843001AGI-22
www.icst.com/products/hiperclocks.html
REV. A AUGUST 1, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS843001I-22 is a a highly versatile, low
phase noise LVPECL/LVCMOS Synthesizer
which can generate low jitter reference clocks for
a variety of communications applications and is
a member of the HiPerClocks
TM
family of high
performance clock solutions from ICS. The dual
crystal interface allows the synthesizer to support up to two
communications standards in a given application (i.e. 1GB
Ethernet with a 25MHz crystal and 1Gb Fibre Channel
using a 25.5625MHz cr ystal). The r ms phase jitter
performance is typically less than 1ps, thus making the
device acceptable for use in demanding applications such
as OC48 SONET and 10Gb Ethernet. The ICS843001I-22
is packaged in a small 24-pin TSSOP package.
F
EATURES
One 3.3V or 2.5V LVPECL output pair and
one LVCMOS/LVTTL output
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
VCO range: 490MHz - 640MHz
Output frequency range: 490MHz - 640MHz
Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
RMS phase jitter @ 125MHz (1.875MHz - 20MHz):
0.5ps (typical)
Full 3.3V or 2.5V supply modes
-40C to 85C ambient operating temperature
Available in both, Standard and RoHS/Lead-Free
compliant packages
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
11
10
01
00
00
01
10
11
Phase
Detector
VCO
490MHz -640MHz
000 18
001 22
010 24
011 25
100 32
(default)
101 40
N
000 1
001 2
010 3
011 4
(default)
100 5
101 6
110 8
111 10
M
3
3
OSC
OSC
ICS843001I-22
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
V
CCO
_
LVCMOS
N 0
N 1
N 2
V
CCO
_
LVPECL
Q
nQ
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EE
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CCA
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CC
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1
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4
5
6
7
8
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10
11
12
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SEL0
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23
22
21
20
19
18
17
16
15
14
13
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IAGRAM
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SEL1
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XTAL_OUT0
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XTAL_OUT1
CLK
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OE
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ONTROL
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ABLE
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843001AGI-22
www.icst.com/products/hiperclocks.html
REV. A AUGUST 1, 2005
2
Integrated
Circuit
Systems, Inc.
ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
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C
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843001AGI-22
www.icst.com/products/hiperclocks.html
REV. A AUGUST 1, 2005
3
Integrated
Circuit
Systems, Inc.
ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. C
OMMON
C
ONFIGURATIONS
T
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T
ABLE
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ABLE
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ABLE
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UTPUT
D
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F
UNCTION
T
ABLE
T
ABLE
3D. B
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M
ODE
F
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B
843001AGI-22
www.icst.com/products/hiperclocks.html
REV. A AUGUST 1, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_LVCMOS,
V
CCO_LVPECL
= 3.3V10%, TA = -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
(LVPECL)
Continuous Current
50mA
Surge Current
100mA
Outputs, V
O
(LVCMOS)
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
70C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_LVCMOS,
V
CCO_LVPECL
= 2.5V5%, TA = -40C
TO
85C
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m
843001AGI-22
www.icst.com/products/hiperclocks.html
REV. A AUGUST 1, 2005
5
Integrated
Circuit
Systems, Inc.
ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_LVPECL
= 3.3V10%
OR
2.5V5%, TA = -40C
TO
85C
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_LVCMOS
= 3.3V10%
OR
2.5V5%, TA = -40C
TO
85C
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843001AGI-22
www.icst.com/products/hiperclocks.html
REV. A AUGUST 1, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
7B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_LVCMOS,
V
CCO_LVPECL
= 2.5V5%, TA = -40C
TO
85C
T
ABLE
7A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_LVCMOS,
V
CCO_LVPECL
= 3.3V10%, TA = -40C
TO
85C
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0
0
8
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
Q
n
/
Q
5
4
5
5
%
T
U
O
_
F
E
R
z
H
M
0
5
2
4
4
6
5
%
.
e
c
a
f
r
e
t
n
i
l
a
t
s
y
r
c
a
g
n
i
s
u
r
e
t
t
ij
e
s
a
h
P
:
1
E
T
O
N
T
ABLE
6. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_LVCMOS,
V
CCO_LVPECL
= 3.3V10%, TA = -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
N
I
y
c
n
e
u
q
e
r
F
t
u
p
n
I
K
L
C
0
=
0
L
E
S
,
1
=
1
L
E
S
4
1
5
5
.
5
3
z
H
M
0
=
0
L
E
S
,
1
=
1
L
E
S
C
D
0
5
2
z
H
M
843001AGI-22
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REV. A AUGUST 1, 2005
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ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.5ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
Phase Noise Result by adding a
10Gb Ethernet Filter to raw data
Raw Phase Noise Data
10Gb Ethernet Filter
dBc
Hz
N
OISE
P
O
WER
843001AGI-22
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REV. A AUGUST 1, 2005
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F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V LVPECL O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V0.33V
LVCMOS O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
V
EE
3.3V LVCMOS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.6510%
-1.65V10%
V
EE
RMS P
HASE
J
ITTER
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
2.5V LVCMOS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-0.5V 0.125V
V
EE
2.5V LVPECL O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
V
EE
V
CC,
V
CCA,
V
CCO_LVPECL
V
CC,
V
CCA,
V
CCO_LVCMOS
V
CC,
V
CCA,
V
CCO_LVPECL
V
CC,
V
CCA,
V
CCO_LVCMOS
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
V
CCO_LVCMOS
2
t
PW
REF_OUT
843001AGI-22
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REV. A AUGUST 1, 2005
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ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q
LVPECL O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
LVPECL O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
nQ
LVCMOS O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
843001AGI-22
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REV. A AUGUST 1, 2005
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ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843001I-22 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
ICS843001I-22
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843001I-22 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO_x
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V or 2.5V
.01
F
V
CC
843001AGI-22
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ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
outputs are designed to drive 50
transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion.
Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the CLK input to
ground.
C
ONTROL
P
INS
:
All
control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
843001AGI-22
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REV. A AUGUST 1, 2005
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ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 4A and Figure 4B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to ter-
minating 50
to V
CC
- 2V. For V
CCO
= 2.5V, the V
CCO
- 2V is very
close to ground level. The R3 in Figure 4B can be eliminated
and the termination is shown in
Figure 4C.
F
IGURE
4C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
4B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
4A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
843001AGI-22
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REV. A AUGUST 1, 2005
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Integrated
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ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001I-22.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001I-22 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 160mA = 554.4mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 554.4mW + 30mW = 584.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used.
Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 8
below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.584W * 65C/W = 123C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
T
ABLE
8. T
HERMAL
R
ESISTANCE
JA
FOR
24-
PIN
TSSOP, F
ORCED
C
ONVECTION
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843001AGI-22
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ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a
termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
5. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
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ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843001I-22 is: 3881
T
ABLE
9.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843001AGI-22
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REV. A AUGUST 1, 2005
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Integrated
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ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
24 L
EAD
TSSOP
T
ABLE
10. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
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e
t
e
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i
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i
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m
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843001AGI-22
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REV. A AUGUST 1, 2005
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Integrated
Circuit
Systems, Inc.
ICS843001I-22
F
EMTO
C
LOCKS
TM C
RYSTAL
/LVCMOS-
TO
-
3.3V, 2.5V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
11. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
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The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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