ICS487-25
MDS 487-25 A
1
Revision 050604
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 297-1201
l
www.icst.com
Quad PLL for DTV
Description
The ICS487-25 generates five high-quality,
high-frequency clock outputs. It is designed to replace
crystals and crystal oscillators in DTV applications.
Using ICS' patented Phase Locked Loop (PLL)
techniques, the device runs from a lower frequency
crystal or clock input.
Because there is zero ppm frequency synthesis error
on the audio clocks, the audio will remain locked to the
video.
Features
Packaged in 16-pin TSSOP
Available in Pb-free packaging
Replaces multiple crystals and oscillators
Input crystal or clock frequency of 27 MHz
Zero ppm frequency synthesis error
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low power CMOS process
Block Diagram
X1/ICLK
X2
PLL1
PLL2
Crystal
Oscillator/
Clock
Buffer
27 MHz
clock or
crystal
input
External capacitors
may be required.
VDD
GND
PDTS
(all outputs and PLLs)
20M
ACLK
3
3
PLL3
33.0M
PLL4
24.576M
S1:0
2
48M
Quad PLL for DTV
MDS 487-25 A
2
Revision 050604
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 297-1201
l
www.icst.com
ICS487-25
Pin Assignment
ACLK Output Selection Table
Note: When S1 and S0 are switched, all other output
clocks will remain stable throughout the transition.
Pin Descriptions
12
1
11
2
10
3
9
X1/ICLK
4
S0
5
S1
6
VDD
7
48M
8
VDD
PDTS
GND
VDD
GND
GND
ACLK
20M
33.0M
16
15
14
13
24.576M
X2
16 pin (173 mil) TSSOP
S1
S0
ACLK (MHz)
0
0
18.432
0
1
16.9344
1
0
12.288
1
1
18.432
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1/ICLK
Input
Crystal connection. Connect to 27 MHz crystal or clock input.
2
S0
Input
Select pin 0. Determines ACLK output frequency per table above.
Internal pull up resistor.
3
S1
Input
Select pin 1. Determines ACLK output frequency per table above.
Internal pull up resistor.
4
48M
Output
48 MHz clcok output. Weak internal pull-down when tri-state.
5
VDD
Power
Connect to +3.3 V.
6
GND
Power
Connect to ground.
7
20M
Output
20 MHz clock output. Weak internal pull-down when tri-state.
8
24.576M
Output
24.576 MHz clock output. Weak internal pull-down when tri-state.
9
ACLK
Output
Audio clock output. Determined by table above. Weak internal
pull-down when tri-state
10
33.0M
Output
33.0 MHz clock output. Weak internal pull-down when tri-state.
11
GND
Power
Connect to ground.
12
VDD
Power
Connect to +3.3 V.
13
GND
Power
Connect to ground.
14
PDTS
Input
Powers down entire chip and tri-states outputs when low. Internal
pull-up resistor.
15
VDD
Power
Connect to +3.3 V.
16
X2
Input
Connect to 27 MHz crystal or float for clock input.
Quad PLL for DTV
MDS 487-25 A
3
Revision 050604
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 297-1201
l
www.icst.com
ICS487-25
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS487-25 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal
(C
L
-6 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33
series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS487-25. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS487-25. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70
C
Quad PLL for DTV
MDS 487-25 A
4
Revision 050604
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 297-1201
l
www.icst.com
ICS487-25
Recommended Operation Conditions
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70
C
Storage Temperature
-65 to +150
C
Junction Temperature
125
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.135
+3.3
+3.465
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.135
3.3
3.465
V
Supply Current
IDD
No load, PDTS=1
35
mA
Power Down Current
IDDPD
No load, PDTS=0
20
A
Input High Voltage
V
IH
2
V
Input Low Voltage
V
IL
0.8
V
Output High Voltage
V
OH
I
OH
= -4 mA
VDD-0.4
V
Output High Voltage
V
OH
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 12 mA
0.4
V
Short Circuit Current
I
OS
Clock outputs
70
mA
Input Capacitance, inputs
C
IN
5
pF
Nominal Output Impedance
Z
OUT
20
Internal Pull-up Resistor
R
PU
S1, S0, PDTS pins
360
k
Internal Pull-down Resistor
R
PD
Clock outputs
510
k
Item
Rating
Quad PLL for DTV
MDS 487-25 A
5
Revision 050604
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 297-1201
l
www.icst.com
ICS487-25
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70
C
Note 1: Measured with a 15 pF load.
Thermal Characteristics
Marking Diagram
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week
number that the part was assembled.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
f
IN
27
MHz
Output Rise Time
t
OR
20% to 80%, Note 1
1.2
ns
Output Fall Time
t
OF
80% to 20%, Note 1
1.0
ns
Output Clock Duty Cycle
at VDD/2, Note 1
45
50
55
%
Absolute Clock Period Jitter
Note 1
175
ps
Frequency Synthesis Error
All outputs
0
ppm
Output Enable Time
t
OE
PDTS high to output
locked to 1%
250
s
Output Disable Time
t
OD
PDTS low to tri-state
20
ns
Audio Clock Stabilization Time
Time from a change
in S1 or S0 until
output stable within
1%
50
s
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
78
C/W
JA
1 m/s air flow
70
C/W
JA
3 m/s air flow
68
C/W
Thermal Resistance Junction to Case
JC
37
C/W
1
8
9
16
487G-25
######
YYWW$$
Quad PLL for DTV
MDS 487-25 A
6
Revision 050604
Integrated Circuit Systems
l
525 Race Street, San Jose, CA 95126
l
tel (408) 297-1201
l
www.icst.com
ICS487-25
Package Outline and Package Dimensions
(16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS487G-25
487G-25 (1st line)
YYWW$$ (3rd line)
Tubes
16-pin TSSOP
0 to +70
C
ICS487G-25T
Tape and Reel
16-pin TSSOP
0 to +70
C
ICS487G-25LF
487G-25LF (1st line)
YYWW$$ (3rd line)
Tubes
16-pin TSSOP
0 to +70
C
ICS487G-25LFT
Tape and Reel
16-pin TSSOP
0 to +70
C
IN D E X
A R E A
1 2
16
D
E 1
E
S E A T IN G
P LA N E
A
1
A
A
2
e
- C -
b
aaa
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.1
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
0
8
0
8
aaa
--
0.10
--
0.004
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