ICS525-01/02/11/12
MDS 525-01/02/11/12 Q
1
Revision 101105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
User Configurable Clock
Description
The ICS525-01/02/11/12 are the most flexible way to
generate a high-quality, high-accuracy, high-frequency
clock output from an inexpensive crystal or clock input.
The user can configure the device to produce nearly
any output frequency from any input frequency by
grounding or floating the select pins. Neither
microcontroller, software, nor device programmer are
needed to set the frequency. Using Phase-Locked
Loop (PLL) techniques, the device accepts a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 250 MHz. It can also produce a
highly accurate output clock from a given input clock,
keeping them frequency locked together.
For similar capability with a serial interface, use the
ICS307. For simple multipliers to produce common
frequencies, refer to the ICS50x family of parts, which
are smaller and more cost effective.
These products are intended for clock generation. They
have low output jitter (variation in the output period), but
input to output skew and jitter are not defined nor
guaranteed. For applications which require defined
input to output timing, use the ICS527-01.
Features
Packaged as 28-pin SSOP (150 mil body)
Industrial and commercial versions available in Pb
(lead) free package
User determines the output frequency by setting all
internal dividers
Eliminates need for custom oscillators
No software needed
Online calculator determines register settings
Pull-ups on all select inputs
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Very low jitter
Duty cycle of 45/55 up to 200 MHz
Operating voltage of 3.0 V or 5.5 V
Ideal for oscillator replacement
Industrial temperature version available
For Zero Delay, refer to the ICS527
Block Diagram
VDD
GND
2
2
CLK
REF
Reference
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
VCO
Divider
Output
Divider
9
7
3
R6:R0
V8:V0
S2:S0
X1/ICLK
X2
Crystal or clock
input
Optional crystal capacitors
Crystal
Oscillator
PD
User Configurable Clock
MDS 525-01/02/11/12 Q
2
Revision 101105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12
Pin Assignment
Pin Descriptions
KEY: I(PU) = Input with internal pull-up resistor; X1, X2 = crystal connections
18
7
17
8
16
9
15
X1/ICLK
10
X2
11
GND
12
CLK
13
V0
14
V1
GND
PD
V8
V2
V7
V5
V3
V6
22
21
20
19
V4
REF
5
6
S2
VDD
VDD
24
23
R0
3
4
S0
S1
R1
26
25
R2
1
2
R5
R6
R3
28
27
R4
ICS525-01/-02/-11/-12
Pin
Number
Pin
Name
Pin
Type
Pin Description
1, 2,
24-28
R5, R6,
R0-R4
I(PU)
Reference divider word input pins determined by user. Forms a binary number from 0
to 127.
3, 4, 5
S0, S1, S2
I(PU)
Select pins for output divider determined by user. See table on page 3
6, 23
VDD
Power
Connect to VDD.
7
X1/ICLK
X1
Crystal connection. Connect to a parallel resonant fundamental crystal or input clock.
8
X2
X2
Crystal connection. Connect to a crystal or leave unconnected for clock.
9, 20
GND
Power
Connect to ground.
10 - 18
V0 - V8
I(PU)
VCO divider word input pins determined by user. Forms a binary number from 0 to
511.
19
PD
Input
Power-down. Active low. Turns off entire chip when low. Clock outputs stop low.
21
CLK
Output
Output clock determined by status of R0-R6, V-V8, S0-S2, and input frequency.
22
REF
Output
Reference output. Buffered crystal oscillator (or clock ) output.
User Configurable Clock
MDS 525-01/02/11/12 Q
3
Revision 101105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12
ICS525-01 Output Frequency and Output Divider Table
ICS525-02 Output Frequency and Output Divider Table
ICS525-11 Output Frequency and Output Divider Table
S2
Pin 5
S1
Pin 4
S0
Pin 3
CLK Output
Divider
Output Frequency Range (MHz)
VDD = 5 V
VDD = 3.3 V
0 - 70
C
-40 to +85
C
0 - 70
C
-40 to +85
C
0
0
0
10
326
323
318
316
0
0
1
2
15160
15140
15100
1590
0
1
0
8
3.7540
3.7536
3.7525
3.7522
0
1
1
4
7.580
7.572
7.550
7.545
1
0
0
5
650
645
634
630
1
0
1
7
440
436
426
423
1
1
0
9
3.333.3
3.330
3.320
3.318
1
1
1
6
553
547
527
524
S2
Pin 5
S1
Pin 4
S0
Pin 3
CLK Output
Divider
Output Frequency Range (MHz)
VDD = 5 V
VDD = 3.3 V
-40 to +85
C
-40 to +85
C
0
0
0
6
567
540
0
0
1
2
15200
15120
0
1
0
8
3.7550
3.7530
0
1
1
4
7.5100
7.560
1
0
0
5
680
648
1
0
1
7
457
434
1
1
0
1
30250
30200
1
1
1
3
10133
1080
S2
Pin 5
S1
Pin 4
S0
Pin 3
CLK Output
Divider
Output Frequency Range (MHz)
VDD = 5 V
VDD = 3.3 V
0 - 70
C
-40 to +85
C
0 - 70
C
-40 to +85
C
0
0
0
10
0.756.5
0.755.75
0.754.5
0.754
0
0
1
2
3.7540
3.7535
3.7525
3.7522.5
0
1
0
8
0.9410
0.949
0.946.25
0.945.5
0
1
1
4
1.87520
1.87518
1.87512.5
1.87511.25
1
0
0
5
1.512.5
1.511.25
1.58.5
1.57.5
1
0
1
7
110
19
16.5
15.75
1
1
0
9
0.838.33
0.837.5
0.835
0.834.5
1
1
1
6
1.2513.25
1.2511.75
1.256.75
1.256
User Configurable Clock
MDS 525-01/02/11/12 Q
4
Revision 101105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12
ICS525-12 Output Frequency and Output Divider Table
S2
Pin 5
S1
Pin 4
S0
Pin 3
CLK Output
Divider
Output Frequency Range (MHz)
VDD = 5 V
VDD = 3.3 V
-40 to +85
C
-40 to +85
C
0
0
0
6
1.2516.75
1.2510
0
0
1
2
3.7550
3.7530
0
1
0
8
0.9412.5
0.947.5
0
1
1
4
1.87525
1.87515
1
0
0
5
1.520
1.512
1
0
1
7
114.25
18.5
1
1
0
1
7.562.5
7.550
1
1
1
3
2.533.25
2.520
User Configurable Clock
MDS 525-01/02/11/12 Q
5
Revision 101105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12
External Components/Crystal
Selection
Decoupling Capacitors
The ICS525-01/02/11/12 requries two 0.01F
decoupling capacitors to be connected between VDD
and GND, one on each side of the chip. The capacitor
must be connected close to the device to minimize lead
inductance.
External Resistors
A 33
series termination resistor should be used on
the CLK and REF pins.
Crystal Load Capacitors
The approximate total on-chip capacitance for a crystal
is 16 pF, so a parallel resonant, fundamental mode
crystal with this value of load (correlation) capacitance
should be used. For crystals with a specified load
capacitance greater than 16 pF, crystal capacitors may
be connected from each of the pins X1 and X2 to
Ground as shown in the block diagram. The value (in
pF) of these crystal caps should be (CL -16)*2, where
CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to
X1 and leave X2 unconnected (no capacitors on
either).
Determining the Output Frequency
Users have full control in setting the desired output
frequency over the range shown in the tables on pages
3-4. To replace a standard oscillator, users should
connect the divider select input pins directly to ground
(or VDD, although this is not required because of
internal pull-ups) during Printed Circuit Board layout.
The ICS525 will automatically produce the correct
frequency when all components are soldered. It is also
possible to connect the inputs to parallel I/O ports to
switch frequencies. By choosing divides carefully, the
number of inputs which need to be changed can be
minimized. Observe the restrictions on allowed values
of VDW and RDW.
Configuration Pin Settings
The output of the ICS525 can be determined by the
following simple equation:
Where:
Reference Divider Word (RDW) = 0 to 127 (0 not
permitted for ICS525-01/-11)
VCO Divider Word (VDW) = 0 to 511 (0, 1, 2, 3 not
permitted for ICS525-01/-11)
Output Divider (OD) = values on pages 3-4
Also, the following operating ranges should be
observed:
1. The output frequency must be in the ranges listed on
pages 3-4.
2. The phase detector frequency must be above 200
kHz.
Since all of the inputs have pull-up resistors, it is only
necessary to ground the pins that need to be set to
zero.
Which Part to Use?
The ICS525-01 is the original configurable clock.
The ICS525-02 has a higher maximum output
grequency and a slightly different set of output dividers.
The ICS525-11 has the same divider set as the -01 but
is optimized for low frequency operation.
The ICS525-12 has the same divider set as the -02 but
is optimized for low frequency operation.
To determine the best combination of VCO, reference,
and output divide, use the ICS525 Calculator on our
web site.
CLK
Frequency
Input Frequency
2x
VDW 8
+
(
)
RDW 2
+
(
) OD
---------------------------------------------
=
200kHz InputFrequency
RDW 2
+
(
)
-----------------------------------------------
<
User Configurable Clock
MDS 525-01/02/11/12 Q
6
Revision 101105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS525-01/02/11/12. These
ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional
operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
can affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature, Commercial
0 to +70
C
Ambient Operating Temperature, Industrial
-40 to +85
C
Storage Temperature
-65
C to 150C
Junction Temperature
125
C
Soldering Temperature
260
C (max. of 10 seconds)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
5.5
V
Operating Supply Current
IDD
60 MHz out, no load,
15 MHz crystal,
ICS525-01/02 only
8
mA
Operating Supply Current
IDD
40 MHz out, 15 MHz
crystal, ICS525-11/12
only
6
mA
Operating Supply Current,
Power-down
IDD
Pin 19 = 0, Note 1
4
A
Input High Voltage
V
IH
2
V
Input Low Voltage
V
IL
0.8
V
Input High Voltage,
X1/ICLK only
V
IH
ICLK (pin7)
VDD/2+1
VDD/2
V
Input Low Voltage, X1/ICLK
only
V
IL
ICLK (pin7)
VDD/2
VDD/2-1
V
Output High Voltage
V
OH
I
OH
= -12 mA
VDD-0.4
V
Output Low Voltage
V
OL
I
OL
= 12 mA
0.4
V
User Configurable Clock
MDS 525-01/02/11/12 Q
7
Revision 101105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V
Short Circuit Current
CLK and REF outputs
55
mA
Input Capacitance
C
IN
V, R, S pins and pin 19
4
pF
On-chip Pull-up Resistor
R
PU
V, R, S pins and pin 19
270
k
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
F
IN
Crystal input
5
27
MHz
Clock input
2
50
MHz
Output Clock Rise Time
0.8 to 2.0 V
1
ns
Output Clock Fall Time
2.0 to 0.8 V
1
ns
Output Clock Duty Cycle, OD =
2, 4, 6, 8, or 10
At VDD/2
45
49 to
51
55
%
Output Clock Duty Cycle, OD =
3, 5, 7, or 9
At VDD/2
40
60
%
Output Clock Duty Cycle, OD =
1 (-02 and -12 only)
At VDD/2
35
65
Power-down Time, PD low to
clocks stopped
50
ns
Power-up Time, PD high to
clocks stable
10
ms
Absolute Clock Period Jitter,
ICS525-01, Note 2
t
ja
Deviation from mean
140
ps
One Sigma Clock Period Jitter,
ICS525-01, Note 2
t
js
One Sigma
45
ps
Absolute Clock Period Jitter,
ICS525-02, Note 2
t
ja
Deviation from mean
85
ps
One Sigma Clock Period Jitter,
ICS525-02, Note 2
t
js
One Sigma
30
ps
Absolute Clock Period Jitter,
ICS525-11, Note 2
t
ja
Deviation from mean
160
ps
One Sigma Clock Period Jitter,
ICS525-11, Note 2
t
js
One Sigma
40
ps
Absolute Clock Period Jitter,
ICS525-12, Note 2
t
ja
Deviation from mean
160
ps
One Sigma Clock Period Jitter,
ICS525-12, Note 2
t
js
One Sigma
40
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
User Configurable Clock
MDS 525-01/02/11/12 Q
8
Revision 101105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12
NOTE 1: Phase relationship between input and output can change at power-up. For a fixed phase
relationship, see the ICS527.
NOTE 2: For 16 MHz, 100 MHz output. Use the -02 for lowest jitter.
Package Outline and Package Dimensions
(28-pin SSOP, 150 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
INDEX
AREA
1 2
28
D
E1
E
SEATING
PLANE
A
1
A
A
2
e
- C -
b
aaa
C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters
Inches*
Symbol
Min
Max
Min
Max
A
1.35
1.75
.053
.069
A1
0.10
0.25
.0040
.010
A2
--
1.50
--
.059
b
0.20
0.30
.008
.012
C
0.18
0.25
.007
.010
D
9.80
10.00
.386
.394
E
5.80
6.20
.228
.244
E1
3.80
4.00
.150
.157
e
0.635 Basic
0.025 Basic
L
0.40
1.27
.016
.050
0
8
0
8
aaa
--
0.10
--
0.004
User Configurable Clock
MDS 525-01/02/11/12 Q
9
Revision 101105
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS525-01/02/11/12
Ordering Information
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS525-01R
ICS525-01R
Tubes
28-pin SSOP
0 to +70
C
ICS525-01RT
ICS525-01R
Tape and Reel
28-pin SSOP
0 to +70
C
ICS525-01RLF
ICS525-01RLF
Tubes
28-pin SSOP
0 to +70
C
ICS525-01RLFT
ICS525-01RLF
Tape and Reel
28-pin SSOP
0 to +70
C
ICS525-01RI
ICS525-01RI
Tubes
28-pin SSOP
-40 to +85
C
ICS525-01RIT
ICS525-01RI
Tape and Reel
28-pin SSOP
-40 to +85
C
ICS525-01RILF
ICS525-01RILF
Tubes
28-pin SSOP
-40 to +85
C
ICS525-01RILFT
ICS525-01RILF
Tape and Reel
28-pin SSOP
-40 to +85
C
ICS525R-02I
ICS525R-02I
Tubes
28-pin SSOP
-40 to +85
C
ICS525R-02IT
ICS525R-02I
Tape and Reel
28-pin SSOP
-40 to +85
C
ICS525R-02ILF
ICS525R-02ILF
Tubes
28-pin SSOP
-40 to +85
C
ICS525R-02ILFT
ICS525R-02ILF
Tape and Reel
28-pin SSOP
-40 to +85
C
ICS525R-11
ICS525R-11
Tubes
28-pin SSOP
0 to +70
C
ICS525R-11T
ICS525R-11
Tape and Reel
28-pin SSOP
0 to +70
C
ICS525R-11LF
ICS525R-11LF
Tubes
28-pin SSOP
0 to +70
C
ICS525R-11LFT
ICS525R-11LF
Tape and Reel
28-pin SSOP
0 to +70
C
ICS525RI-11
ICS525RI-11
Tubes
28-pin SSOP
-40 to +85
C
ICS525RI-11T
ICS525RI-11
Tape and Reel
28-pin SSOP
-40 to +85
C
ICS525RI-11LF
ICS525RI-11LF
Tubes
28-pin SSOP
-40 to +85
C
ICS525RI-11LFT
ICS525RI-11LF
Tape and Reel
28-pin SSOP
-40 to +85
C
ICS525RI-12
ICS525RI-12
Tubes
28-pin SSOP
-40 to +85
C
ICS525RI-12T
ICS525RI-12
Tape and Reel
28-pin SSOP
-40 to +85
C
ICS525RI-12LF
ICS525RI-12LF
Tubes
28-pin SSOP
-40 to +85
C
ICS525RI12LFT
ICS525RI-12LF
Tape and Reel
28-pin SSOP
-40 to +85
C
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