ICS527-02
MDS 527-02 F
1
Revision 022806
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
Clock Slicer User Configurable PECL Input Zero Delay Buffer
Description
The ICS527-02 Clock Slicer is the most flexible way to
generate a CMOS output clock from a PECL input
clock with zero skew. The user can easily configure the
device to produce nearly any output clock that is
multiplied or divided from the input clock. The part
supports non-integer multiplications and divisions. A
SYNC pulse indicates when the rising clock edges are
aligned with zero skew. Using Phase-Locked Loop
(PLL) techniques, the device accepts an input clock up
to 200 MHz and produces an output clock up to 160
MHz.
The ICS527-02 aligns rising edges on PECLIN with
FBIN at a ratio determined by the reference and
feedback dividers.
For a PECL input and output clock with zero delay, use
the ICS527-04.
For a CMOS input and PECL output with zero delay,
use the ICS527-03.
Features
Packaged as 28-pin SSOP (150 mil body)
Synchronizes fractional clocks rising edges
PECL IN to CMOS OUT
Pin selectable dividers
Zero input to output skew
User determines the output frequency--no software
needed
Slices frequency or period
Input clock frequency of 1.5 MHz to 200 MHz
Output clock frequencies from 2.5 MHz to 160 MHz
Very low jitter
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low-power CMOS process
Industrial temperature version available
Block Diagram
PECLIN
VDD
GND
2
2
CLK1
CLK2
Reference
Divider
PECLIN
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
Output
Divider
7
7
2
R6:R0
F6:F0
S1:S0
PDTS
Feedback
Divider
FBIN
1
0
Divide
by 2
SYNC
DIV2
Feedback can
come from
CLK1 or CLK2
(not both)
33 ohm
33 ohm
Clock Slicer User Configurable PECL Input Zero Delay Buffer
MDS 527-02 F
2
Revision 022806
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS527-02
Pin Assignment
28-pin 150 mil body SSOP
Output Frequency Range Table
CLK2 Operation Table
Pin Descriptions
1 8
7
1 7
8
1 6
9
1 5
P E C L IN
1 0
P E C L IN
1 1
G N D
1 2
C L K 2
1 3
O E C L K 2
1 4
F 0
G N D
P D T S
F B IN
F 1
F 6
F 4
F 2
F 5
2 2
2 1
2 0
1 9
F 3
C L K 1
5
6
S 1
V D D
V D D
2 4
2 3
R 0
3
4
D IV 2
S 0
R 1
2 6
2 5
R 2
1
2
R 5
R 6
R 3
2 8
2 7
R 4
S1 S0
Output Frequency (MHz)
Commercial
Industrial
0
0
10 - 50
16 - 45
0
1
5 - 40
8 - 33
1
0
4 - 10
4 - 8
1
1
20 -160
32 - 140
OECLK2
DIV2
CLK2
0
X
Z
1
0
SYNC
1
1
CLK1/2
Pin
Number
Pin
Name
Pin
Type
Pin Description
1,2, 24-28
R5, R6,
R0-R4
Input
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
3
DIV2
Input
Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based
on the table above. Internal pull-up.
4, 5
S0, S1
Input
Select pins for output divider determined by user. See table above. Internal
pull-up.
6, 23
VDD
Power
Connect to +3.3 V.
7
PECLIN
Input
True PECL input clock.
8
PECLIN
Input
Complementary PECL input clock.
9, 20
GND
Power
Connect to ground
10
OECLK2
Input
CLK2 Output Enable. CLK2 tri-stated when low. Internal pull-up.
11-17
F0-F6
Input
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
18
FBIN
Input
Feedback clock input
19
PDTS
Input
Power Down. Active low. Turns off entire chip when low, both clock outputs are
tri-stated. Internal pull-up.
21
CLK2
Output
Output clock 2. Can be SYNC pulse or a low skew divide by 2 of CLK1.
22
CLK1
Output
Output clock 1.
Clock Slicer User Configurable PECL Input Zero Delay Buffer
MDS 527-02 F
3
Revision 022806
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS527-02
External Components
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS527-02 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. The
capacitor must be connected close to the device to
minimize lead inductance.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Using the ICS527-02 Clock Slicer
First use DIV2 to select the function of the CLK2
output. If DIV2 is high, a divide by 2, low skew version
of CLK1 is present on CLK2. If DIV2 is low, a SYNC
pulse is generated on CLK2. The SYNC pulse goes
high synchronously with the rising edges of PECLIN
and CLK1 that are de-skewed. The SYNC function
operates at CLK1 frequencies up to 66 MHz. If neither
CLK1/2 or a SYNC pulse are required, then CLK2
should be disabled by connecting OECLK2 to ground.
This will also give the lowest jitter on CLK1.
Next, the feedback scheme should be chosen. If CLK2
is being used as a SYNC pulse, or is tri-stated, then
CLK1 must be connected to FBIN. If CLK2 is selected
to be CLK1/2 (DIV2=1, OECLK2=1) then either CLK1
or CLK2 must be connected to FBIN. The choice
between CLK1 or CLK2 is illustrated by the following
examples where the device has been configured to
generate CLK1 that is twice the frequency on PECLIN.
Using CLK1 as feedback will always result in
synchronized rising edges between PECLIN and CLK1
if CLK1 is used as feedback. CLK2 could be a falling
edge compared to PECLIN. Therefore, wherever
possible it is recommended to use CLK2 for feedback,
which will synchronize the rising edges of all three
clocks.
More complicated feedback schemes can be used,
such as incorporating multiple output buffers in the
feedback path. An example is given later in the
datasheet. The fundamental property of the ICS527-02
is that it aligns rising edges on PECLIN and FBIN at a
ratio determined by the reference and feedback
dividers.
Set S1 and S0 (page 2) based on the output frequency.
Lastly, the divider settings should be selected. This is
described in the following section.
Determining ICS527-02 Divider Settings
The user has full control in setting the desired output
clock over the range shown in the table on page 2. The
user should connect the divider select input pins
directly to ground (or VDD, although this is not required
because of internal pull-ups) during Printed Circuit
Board layout, so the ICS527-02 automatically produces
P E C L IN
C L K 1 F e e d b a c k
C L K 1
C L K 2
p h a s e is
in d e t e r m in a t e
P E C L IN
P E C L I N
C L K 1
C L K 2
C L K 2 F e e d b a c k
P E C L I N
Clock Slicer User Configurable PECL Input Zero Delay Buffer
MDS 527-02 F
4
Revision 022806
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS527-02
the correct clock when mounted on the board. It is also
possible to connect the inputs to parallel I/O ports in
order to switch frequencies.
The output of the ICS527-02 can be determined by the
following simple equation:
Where:
Reference Divider Word (RDW) = 0 to 127
Feedback Divider Word (FDW) = 0 to 127
FB Frequency is the same as either CLK1 or
CLK2 depending on feedback connection
Also, the following operating ranges should be
observed:
S0 and S1 should be selected depending on the
frequency of CLK1. The table on page 2 gives the
ranges.
The dividers are expressed as integers. For example, if
a 50 MHz output on CLK1 is desired from a 40 MHz
input, the reference divider word (RDW) should be 2
and the feedback divider word (FDW) should be 3
which gives the required 5/4 multiplication. If multiple
choices of dividers are available, then the lowest
numbers should be used. In this example, the output
divide (OD) should be selected to be 2. Then R6:R0 is
0000010, F6:F0 is 0000011 and S1:S0 is 00. Also, this
example assumes CLK1 is connected to FBIN.
If you need assistance determining the optimum divider
settings, please send an e-mail to
mk-support@icst.com with the desired input clock and
the desired output frequency.
Typical Example
The layout diagram below will produce the waveforms shown on the right.
Note: The series termination resistor is located before the feedback trace
FB Frequency
Input Frequency
FDW
2
+
RDW
2
+
------------------------
=
300kHz
Input Frequency
RDW
2
+
-------------------------------------------
20 MHz
<
<
40 MHz
PECLIN
50 MHz
CLK1
SYNC
CLK2
PECLIN
FBIN
PECLIN
F6
F5
GND
F4
OECLK2
F0
F1
F2
F3
CLK1
CLK2
GND
S1
VDD
R0
VDD
DIV2
S0
R2
R1
R5
R6
R4
R3
PECLIN
PDTS
50 MHz
SYNC
33
33
0.01
F
40 MHz
40 MHz
0.01
F
VDD
Clock Slicer User Configurable PECL Input Zero Delay Buffer
MDS 527-02 F
5
Revision 022806
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS527-02
Multiple Output Example
In this example, an input clock of 125 MHz is used. Eight copies of 50 MHz are required as are eight copies
of 25 MHz, de-skewed and aligned to the 125 MHz input clock. The following solution uses the
MK74CB217 which has dual 1 to 8 buffers with low pin-to-pin skew.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via's should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
2) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock outputs.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS527-02. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
FBIN
PECLIN
F6
F5
GND
F4
OECLK2
F0
F1
F2
F3
CLK1
CLK2
GND
S1
VDD
R0
VDD
DIV2
S0
R2
R1
R5
R6
R4
R3
PECLIN
PDTS
0.01
F
125 MHz
125 MHz
0.01
F
VDD
QB5
QA3
QB6
QB7
OEB
GND
QA5
QA6
QA7
OEA
QB3
QB4
GND
VDD
VDD
VDD
VDD
QA1
QA2
QB1
QB2
INA
QA0
INB
QB0
QA4
GND
GND
0.01
F
0.01
F
MK74C
B217
I
C
S
527-
02
The layout design above produces the waveforms shown below. Note: Series terminating resistors are not shown.
25M
50M
125 M H z,
P E C LIN
25 M H z,
Q A 0-7
50 M H z,
Q B 0-7
P E C LIN not show n
Clock Slicer User Configurable PECL Input Zero Delay Buffer
MDS 527-02 F
6
Revision 022806
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS527-02
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS527-02. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature 0 to +70
C
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
-40 to +85
C
Storage Temperature
-65 to +150
C
Junction Temperature
125
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature, ICS527R-02
0
+70
C
Ambient Operating Temperature, ICS527R-02I
-40
+85
C
Power Supply Voltage (measured in respect to GND)
+3.135
+3.3
+3.465
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.135
3.3
3.465
V
Supply Current
IDD
15 MHz in, 60 MHz
out, no load
18
mA
Supply Current, Power Down
IDDPD
PDTS=0
20
A
Input High Voltage
V
IH
2
V
Input Low Voltage
V
IL
0.8
V
Input Voltage, peak-to-peak
PECLIN, PECLIN
0.3
1
V
Common Mode Range
PECLIN, PECLIN
VDD-1.4
VDD-0.6
V
Output High Voltage
V
OH
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 12 mA
0.4
V
Clock Slicer User Configurable PECL Input Zero Delay Buffer
MDS 527-02 F
7
Revision 022806
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS527-02
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85
C
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.
Input Capacitance
C
IN
Except PECLIN and
FBIN
5
pF
Short Circuit Current
I
OS
70
mA
On-chip pull-up resistor
R
PU
270
k
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
F
IN
1.5
200
MHz
Output Frequency, CLK1
F
OUT
0 to +70
C
2.5
160
MHz
-40 to +85
C
4
140
MHz
Output Rise Time
t
OR
0.8 to 2.0 V, C
L
=15 pF
1
ns
Output Fall Time
t
OF
2.0 to 0.8 V, C
L
=15 pF
1
ns
Output Duty Cycle (% high
time)
t
OD
Measured at VDD/2,
C
L
=15 pF
45
50
55
%
Power Down Time, PDTS low to
clocks tri-stated
50
ns
Power Up Time, PDTS high to
clocks stable
10
ms
Absolute Clock Period Jitter
t
ja
Deviation from mean
90
ps
One sigma Clock Period Jitter
t
js
40
ps
Input to output skew
t
IO
PECLIN to CLK1,
Note 1
-250
250
ps
Device to device skew
t
pi
Common PECLIN,
measured at FBIN
0
500
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Clock Slicer User Configurable PECL Input Zero Delay Buffer
MDS 527-02 F
8
Revision 022806
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS527-02
Package Outline and Package Dimensions
(28-pin SSOP, .150 mil Body, 0.025 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS527R-02
ICS527R-02
Tubes
28-pin SSOP
0 to +70
C
ICS527R-02T
ICS527R-02
Tape and Reel
28-pin SSOP
0 to +70
C
ICS527R-02I
ICS527R-02I
Tubes
28-pin SSOP
-40 to +85
C
ICS527R-02IT
ICS527R-02I
Tape and Reel
28-pin SSOP
-40 to +85
C
INDEX
AREA
1 2
28
D
E1
E
SEATING
PLANE
A
1
A
A
2
e
- C -
b
aaa
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
1.35
1.75
.053
.069
A1
0.10
0.25
.0040
.010
A2
--
1.50
--
.059
b
0.20
0.30
.008
.012
C
0.18
0.25
.007
.010
D
9.80
10.00
.386
.394
E
5.80
6.20
.228
.244
E1
3.80
4.00
.150
.157
e
0.635 Basic
0.025 Basic
L
0.40
1.27
.016
.050
0
8
0
8
aaa
--
0.10
--
0.004
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