ICS548-05C
MDS 548-05C C
1
Revision 020606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
T1/E1 Clock Multiplier
Description
The ICS548-05C is a low-cost, low-jitter,
high-performace clock synthesizer designed to
produce x16 and x24 clocks from T1 and E1
frequencies. Using ICS' patented analog/digital Phase-
Locked Loop (PLL) techniques, the device uses a
crystal or clock input to synthesize popular
communications frequencies. Power down modes allow
the chip to turn off completely, or the PLL and clock
output to be turned off separately.
ICS manuafactures the largest variety of
communications clock synthesizers for all applications.
Consult ICS to eliminate VCXO's, crystals, and
oscillators from your board.
Features
Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Ideal for telecom/datacom chips
Replaces oscillators
3.3 V or 5 V operation
Uses a crystal or clock input
Produces 24.704, 37.056, 32.768, or 49.152 MHz
Includes Power-down features
Advanced, low-power, sub-micron CMOS process
See also the MK2049-34 for generating
Industrial temperature range available
Block Diagram
X1/ICLK
X2
Input
Buffer/
Crystal
Oscillator
1.544 MHz or
2.048 MHz
clock or crystal
input
Optional crystal
capacitors
CLK
REFOUT
MSEL
X16 or x24
PLL/Clock
Synthesis
Circuitry
REFEN
PDCLK
T1/E1 Clock Multiplier
MDS 548-05C C
2
Revision 020606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS548-05C
Pin Assignment
Output Clock Selection Table
Power Down Clock Selection Table
Key: 0 = connect directly to GND; 1 = connect directly
to VDD
Pin Descriptions
Key: XI, XO = crystal connections; the in put pin MSEL must be tied directly to VDD or GND.
For a clock input, connect the input X1 and leave X2 unconnected (floating).
12
1
11
2
10
X1/ICLK
X2
3
9
VDD
4
VDD
DC
5
REFEN
6
REFOUT
7
GND
8
GND
MSEL
GND
PDCLK
GND
DC
VDD
CLK
16
15
14
13
16-pin TSSOP
MSEL
Input (MHz)
CLK (MHz)
Pin 13
PIns 1, (16)
PIn 9
0
1.544
24.704
1
1.544
37.056
0
2.048
32.768
1
2.048
49.152
REFEN PDCLK
Power Down Selection Mode
Pin 4
PIn 11
0
0
The entire chip is off.
0
1
PLL and clock output run, REFOUT low.
1
0
REFOUT running, PLL off, CLK low.
1
1
All running.
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1/ICLK
XI
Crystal connection. Connect this pin to a crystal or clock input.
2, 3, 8
VDD
Power
Connect to +3.3 V or +5 V. All VDD's must be the same.
4
REFEN
Input
Reference Clock Enable. See table above. Connect to GND for best jitter/phase
noise.
5, 6, 7, 12
GND
Power
Connect to ground.
9
CLK
Output
Clock output set by input status of MSEL. See table above.
10, 15
DC
--
Don't Connect. Do not connect these pins to anything.
11
PDCLK
Input
Power down clock. See table above.
13
MSEL
Input
Multiplier select pin. Selects x16 when low, x24 when high.
14
REFOUT
Output
Buffered reference output clock. Controlled by REFEN.
16
X2
XO
Crystal connection. Connect this pin to a crystal or leave unconnected for a clock.
T1/E1 Clock Multiplier
MDS 548-05C C
3
Revision 020606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS548-05C
Application Information
Series Termination Resistor
Clock output traces should use series termination. To
series terminate a 50
trace (a commonly used trace
impedance), place a 33
resistor in series with the
clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
.
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS548-05C must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01F should be connected
between each VDD and GND on pins 3 and 5, as close
to the device as possible Other VDD's can be
connected to pin 3. If reFOUT is not used, then REFEN
should be connected directly to ground.
Crystal Load Capacitors
If a crystal is used, the device crystal connections
should include pads for capacitors from X1 to ground
and from X2 to ground. These capacitors are used to
adjust the stray capacitance of the board to match the
nominally required crystal load capacitance. To reduce
possible noise pickup, use very short PCB traces (and
no vias) been the crystal and device.
The value of the load capacitors can be roughly
determined by the formula C = 2(C
L
- 6) where C is the
load capacitor connected to X1 and X2, and C
L
is the
specified value of the load capacitance for the crystal.
A typical crystal C
L
is 18pF, so C = 2(18 - 6) = 24pF.
Because these capacitors adjust the stray capacitance
of the PCB, check the output frequency using your final
layout to see if the value of C should be changed. For a
clock input, leave X2 unconnected (floating).
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The external crystal should be mounted next to the
device with short traces. The X1 and X2 traces should
not be routed next to each other with minimum spaces,
instead they should be separated and away from other
traces.
3) To minimize EMI and obtain the best signal integrity,
the 33
series termination resistor should be placed
close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS548-05C.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
T1/E1 Clock Multiplier
MDS 548-05C C
4
Revision 020606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS548-05C
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS548-05C. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +70
C
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial)
0 to +70
C
Ambient Operating Temperature (industrial)
-40 to +85
C
Storage Temperature
-65 to +150
C
Junction Temperature
125
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.15
5.5
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Core Operating Voltage
VDD
3.15
5.5
V
Input High Voltage
V
IH
X1/ICLK pin, clock
input only
(VDD/2)+1
VDD/2
V
Input Low Voltage
V
IL
X1/ICLK pin, clock
input only
VDD/2
(VDD/2)-1
V
Input High Voltage
V
IH
2
V
Input Low Voltage
V
IL
0.8
V
Output High Voltage
V
OH
I
OH
= -4 mA
2.4
V
Output High Voltage
V
OH
CMOS level,
I
OH
= -4 mA
VDD-0.4
V
Output Low Voltage
V
OL
I
OL
= 4 mA
0.4
V
Supply Current
IDD
No Load
5
mA
Power Down Supply
Current
IDDPD
No Load
1
A
T1/E1 Clock Multiplier
MDS 548-05C C
5
Revision 020606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS548-05C
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V, Ambient Temperature 0 to +70
C
Thermal Characteristics
Short Circuit Current
I
OS
CLK output
50
mA
Input Capacitance
MSEL, PDCLK,
REFEN
7
pF
Frequency Synthesis Error
Both selections
0
ppm
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Crystal or Clock
Frequency
1.544 or
2.048
MHz
Output Clock Rise Time
t
OR
20% to 80%
1.5
ns
Output Clock Fall Time
t
OF
80% to 20%
1.5
ns
Output Clock Rise Time
t
OR
20% to 80%,
TA = -40 to +85
C
1.7
ns
Output Clock Fall Time
t
OF
80% to 20%,
TA = -40 to +85
C
1.7
ns
Output Clock Duty Cycle
t
OD
At VDD/2
40
50
60
%
Start-up Time
VDD = 3.3 V to CLK
stable
10
ms
Maximum Absolute Jitter,
short term
100
ps
Maximum Absolute Jitter,
short term
TA = -40 to +85
C
150
ps
One Sigma Jitter
25
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
78
C/W
JA
1 m/s air flow
70
C/W
JA
3 m/s air flow
68
C/W
Thermal Resistance Junction to Case
JC
37
C/W
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
T1/E1 Clock Multiplier
MDS 548-05C C
6
Revision 020606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS548-05C
Package Outline and Package Dimensions
(16-pin TSSOP)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Ordering Information
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS548G-05
548G-05
Tubes
16-pin TSSOP
0 to +70
C
ICS548G-05T
548G-05
Tape and Reel
16-pin TSSOP
0 to +70
C
ICS548G-05LF
548G05LF
Tubes
16-pin TSSOP
0 to +70
C
ICS548G-05LFT
548G05LF
Tape and Reel
16-pin TSSOP
0 to +70
C
ICS548G-05I
548G-05I
Tubes
16-pin TSSOP
-40 to +85
C
ICS548G-05IT
548G-05I
Tape and Reel
16-pin TSSOP
-40 to +85
C
INDEX
AREA
1 2
16
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.1
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
0
8
0
8
aaa
--
0.10
--
0.004
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