ICS552-02
MDS 552-02 B
1
Revision 050401
I n t e g r a t e d C i r cu i t S y st e m s
q
5 2 5 Ra ce S t r e e t , S a n J o s e , C A 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. i c s t . c o m
L
OW
S
KEW
2 I
NPUT
MUX
AND
1
TO
8 C
LOCK
B
UFFER
Description
The ICS552-02 is a low skew, single-input to eight-
output clock buffer. It is part of ICS' Clock Blocks
TM
family. See the ICS553 for a 1 to 4 low skew buffer. For
more than 8 outputs see the MK74CBxxx Buffalo
TM
series of clock drivers.
ICS makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
Features
Extremely low skew outputs (50ps maximum)
Packaged in 16 pin TSSOP
Low power CMOS technology
Operating Voltages of 2.5 V to 5 V
Output Enable pin tri-states outputs
5 V tolerant input clocks
Input/Output clock frequency up to 200 MHz
Input clock multiplexer simplifies clock selection
Block Diagram
O E
Q 3
Q 4
Q 2
Q 5
Q 6
Q 1
Q 0
Q 7
IN A
IN B
1
0
S E L A
L
OW
S
KEW
2 I
NPUT
MUX
AND
1
TO
8 C
LOCK
MDS 552-02 B
2
Revision 050401
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
P R E L I M I N A R Y I N F O R M A T I O N
ICS552-02
Pin Assignment
Input Source Select
Pin Descriptions
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of
0.01
F should be connected between VDD on pin 2 and GND on pin 7, and between VDD on pin 15 and
GND on pin 10, as close to the device as possible. A 33
series terminating resistor should be used on
each clock output if the trace is longer than 1 inch.
To achieve the low output skews that the ICS552-02 is capable of, careful attention must be paid to board
layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30
series termination
on one output (with 33
on the others) will cause at least 15ps of skew.
12
1
11
2
10
3
9
OE
4
VDD
5
Q0
6
VDD
7
Q1
8
Q2
Q7
Q6
Q5
Q3
Q4
INA
GND
GND
16
15
14
13
INB
SELA
16 Pin TSSOP
SELA
Input
0
INB
1
INA
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
OE
Input
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
2
VDD
Power
Connect to +2.5V, +3.3V or +5.0V. Must be the same as pin 15.
3
Q0
Output
Clock Output 0
4
Q1
Output
Clock Output 1
5
Q2
Output
Clock Output 2
6
Q3
Output
Clock Output 3
7
GND
Power
Connect to ground.
8
INB
Input
Clock Input B. 5V tolerant input.
9
INA
Input
Clock Input A. 5V tolerant input.
10
GND
Power
Connect to ground.
11
Q4
Output
Clock Output 4
12
Q5
Output
Clock Output 5
13
Q6
Output
Clock Output 6
14
Q7
Output
Clock Output 7
15
VDD
Power
Connect to + 2.5V, +3.3V or +5.0V. Must be the same as pin 2.
16
SELA
Input
Selects either INA or INB. Internal pull-up resistor.
L
OW
S
KEW
2 I
NPUT
MUX
AND
1
TO
8 C
LOCK
MDS 552-02 B
3
Revision 050401
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
P R E L I M I N A R Y I N F O R M A T I O N
ICS552-02
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS552-02. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
VDD=2.5 V 5%
, Ambient temperature 0 to +70
C, unless stated otherwise
Item
Rating
Supply Voltage, VDD
7 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70
C
Storage Temperature
-65 to +150
C
Junction Temperature
175
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+2.375
+5.25
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
2.375
2.625
V
Input High Voltage, INA, INB
V
IH
Note 1
VDD/2+0.5
5.5
V
Input Low Voltage, INA, INB
V
IL
Note 1
VDD/2-0.5
V
Input High Voltage, OE, SELA
V
IH
2
VDD
V
Input Low Voltage, OE, SELA
V
IL
0.4
V
Output High Voltage
V
OH
I
OH
= -16 mA
2
V
Output Low Voltage
V
OL
I
OL
= 16 mA
0.5
V
Operating Supply Current
IDD
No load, 135 MHz
35
mA
Short Circuit Current
I
OS
Each output
60
mA
L
OW
S
KEW
2 I
NPUT
MUX
AND
1
TO
8 C
LOCK
MDS 552-02 B
4
Revision 050401
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
P R E L I M I N A R Y I N F O R M A T I O N
ICS552-02
DC Electrical Characteristics (continued)
VDD=3.3 V 5%
, Ambient temperature 0 to +70
C, unless stated otherwise
VDD=5 V 5%
, Ambient temperature 0 to +70
C, unless stated otherwise
Note: 1. Nominal switching threshold is VDD/2
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.135
3.465
V
Input High Voltage, INA, INB
V
IH
Note 1
VDD/2+0.7
5.5
V
Input Low Voltage, INA, INB
V
IL
Note 1
VDD/2-0.7
V
Input High Voltage, OE, SELA
V
IH
2
VDD
V
Input Low Voltage, OE, SELA
V
IL
0.4
V
Output High Voltage
V
OH
I
OH
= -25 mA
2.4
V
Output Low Voltage
V
OL
I
OH
= 25 mA
0.8
V
Output High Voltage (CMOS
Level)
V
OH
I
OH
= -12 mA
VDD-0.4
V
Operating Supply Current
IDD
No load, 135 MHz
50
mA
Short Circuit Current
I
OS
Each output
80
mA
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
4.75
5.25
V
Input High Voltage, INA, INB
V
IH
Note 1
VDD/2+1
5.5
V
Input Low Voltage, INA, INB
V
IL
Note 1
VDD/2-1
V
Input High Voltage, OE, SELA
V
IH
2
VDD
V
Input Low Voltage, OE, SELA
V
IL
0.4
V
Output High Voltage
V
OH
I
OH
= -45 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 45 mA
0.8
V
Output High Voltage (CMOS
Level)
V
OH
I
OH
= -12 mA
VDD-0.4
V
Operating Supply Current
IDD
No load, 135 MHz
85
mA
Short Circuit Current
I
OS
Each output
100
mA
L
OW
S
KEW
2 I
NPUT
MUX
AND
1
TO
8 C
LOCK
MDS 552-02 B
5
Revision 050401
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
P R E L I M I N A R Y I N F O R M A T I O N
ICS552-02
AC Electrical Characteristics
VDD = 2.5V 5%
, Ambient Temperature 0 to +70
C, unless stated otherwise
VDD = 3.3V 5%
, Ambient Temperature 0 to +70
C, unless stated otherwise
VDD = 5.0V 5%
, Ambient Temperature 0 to +70
C, unless stated otherwise
Notes: 1. With rail-to-rail input clock.
2. Between any two outputs with equal loading.
3. Propagation delay matching through the part.
4. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock
generators.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
0
200
MHz
Output Rise Time
t
OR
0.8 to 2.0 V, C
L
=15 pF
1.5
ns
Output Fall Time
t
OF
2.0 to 0.8 V, C
L
=15 pF
1.5
ns
Propagation Delay
Note 1
3.5
ns
Output to output skew
Note 2
Rising edges at VDD/2
0
50
ps
Input A to Input B skew
Note 3
0
50
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
0
200
MHz
Output Rise Time
t
OR
0.8 to 2.0 V, C
L
=15 pF
1.0
ns
Output Fall Time
t
OF
2.0 to 0.8 V, C
L
=15 pF
1.0
ns
Propagation Delay
Note 1
3.0
ns
Output to output skew
Note 2
Rising edges at VDD/2
0
50
ps
Input A to Input B skew
Note 3
0
50
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
0
200
MHz
Output Rise Time
t
OR
0.8 to 2.0 V, C
L
=15 pF
0.7
ns
Output Fall Time
t
OF
2.0 to 0.8 V, C
L
=15 pF
0.7
ns
Propagation Delay
Note 1
2.8
ns
Output to output skew
Note 2
Rising edges at VDD/2
0
50
ps
Input A to Input B skew
Note 3
0
50
ps
L
OW
S
KEW
2 I
NPUT
MUX
AND
1
TO
8 C
LOCK
MDS 552-02 B
6
Revision 050401
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
P R E L I M I N A R Y I N F O R M A T I O N
ICS552-02
Package Outline and Package Dimensions
(16 pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
Part / Order Number
Marking(both)
Shipping
packaging
Package
Temperature
ICS552G-02
ICS (top line)
Tubes
16 pin TSSOP
0 to +70
C
ICS552G-02T
552G-02 (2nd line)
Tape and Reel
16 pin TSSOP
0 to +70
C
D
E
H
b
e
a
Pin 1
Index
Area
c
A
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
a
0.05
0.15
0.002
0.006
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.0035
0.008
D
4.90
5.10
0.193
0.201
E
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
H
6.40 Basic
0.252 Basic
L
0.45
0.75
0.018
0.030
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