ICS557-06
MDS 557-06 C
1
Revision 010306
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O
NE
TO
F
OUR
HCSL C
LOCK
B
UFFER
Description
The ICS557-06 is a one to four differential clock buffer
designed for use in PCI-Express applications. The
device selects one of the two differential HCSL or LVDS
input pairs and fans out to four pairs of differential
HCSL or LVDS outputs.
Features
Packaged in 20-pin TSSOP
Available in Pb (lead) free package
Operating voltage of 3.3 V
Low power consumption
Input differential clock of up to 200 MHz for HCSL
and up to 100 MHz for LVDS
Jitter 100 ps (peak-to-peak)
Output-to-output skew of 50 ps
Block Diagram
VDD
CLKA
CLKA
Rr (IREF)
CLKB
CLKB
CLKC
CLKC
CLKD
CLKD
SEL
GND
IN1
IN1
IN2
IN2
MUX
2 to 1
OE
2
2
PD
MDS 557-06 C
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ICS557-06
One to Four HCSL Clock Buffer
Pin Assignment
Select Table
Pin Descriptions
13
4
12
5
11
IN2
8
9
10
GND
OE
CLKC
CLKD
GND
CLKD
17
16
IREF
3
IN1
IN1
CLKB
18
CLKB
1
SEL
VDDIN
CLKA
20
CLKA
19
14
2
7
IN2
PD
VDD
CLKC
15
6
20-pin (173 mil) TSSOP
SEL
Input Pair
selected
0
IN2/ IN2
1
IN1/ IN1
Pin
Pin
Name
Pin
Type
Pin Description
1
SEL
Input
SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor.
2
VDDIN
Power
Connect to +3.3 V. Supply voltage for Input clocks.
3
IN1
Input
HCSL/LVDS true input signal 1.
4
IN1
Input
HCSL/LVDS complimentary input signal 1.
5
PD
Input
Powers down the chip and tri-states outputs when low. Internal pull-up resistor.
6
IN2
Input
HCSL/LVDS true input signal 2.
7
IN2
Input
HCSL/LVDS complimentary input signal 2.
8
OE
Input
Provides fast output on, tri-states output (High = enable outputs; Low = disable).
Internal pull-up resistor outputs.
9
GND
Power
Connect to ground.
10
Rr(IREF)
Output
Precision resistor attached to this pin is connected to the internal current reference.
11
CLKD
Output
Differential Complimentary output clock D.
12
CLKD
Output
Differential True output clock D.
13
CLKC
Output
Differential Complimentary output clock C.
14
CLKC
Output
Differential True output clock C.
15
VDDOUT
Power
Connect to +3.3 V. Supply Voltage for Output Clocks.
16
GND
Power
Connect to ground.
17
CLKB
Output
Differential Complimentary output clock B.
18
CLKB
Output
Differential True output clock B.
19
CLKA
Output
Differential Complimentary output clock A.
20
CLKA
Output
Differential True output clock A.
MDS 557-06 C
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ICS557-06
One to Four HCSL Clock Buffer
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS557-06 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Each 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS557-06.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
External Components
A minimum number of external components are
required for proper operation. Decoupling capacitors of
0.01
F should be connected between VDD and GND
pairs (2,9 and 15,16) as close to the device as possible.
Current Reference Source R
r
(Iref)
If board target trace impedance (Z) is 50
, then Rr =
475
(1%), providing IREF of 2.32 mA, output current
(I
OH
) is equal to 6*IREF.
Load Resistors R
L
Since the clock outputs are open source outputs, 50
ohm external resistors to ground are to be connected at
each clock output.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-06 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the PCI-Express Layout Guidelines
section.
The ICS557-06 can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
MDS 557-06 C
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ICS557-06
One to Four HCSL Clock Buffer
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1. Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
2. No vias should be used between decoupling
capacitor and VDD pin.
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the ICS557-06.This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
R
R
475
6*IREF
=2.3 mA
IREF
See Output Termination
Sections - Pages 3 ~ 5
MDS 557-06 C
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ICS557-06
One to Four HCSL Clock Buffer
PCI-Express Layout Guidelines
PCI-Express Device Routing
Typical PCI-Express (HCSL)
Waveform
Common Recommendations for Differential Routing
Dimension or Value
Unit
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
inch
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
L3 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
R
S
33
ohm
R
T
49.9
ohm
Differential Routing on a Single PCB
Dimension or Value
Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
2 min to 16 max
inch
L4 length, Route as coupled stripline 100 ohm differential trace.
1.8 min to 14.4 max
inch
Differential Routing to a PCI Express Connector
Dimension or Value
Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
0.25 to 14 max
inch
L4 length, Route as coupled stripline 100 ohm differential trace.
0.225 min to 12.6 max inch
R
S
R
S
R
T
R
T
PCI-Express
Load or
Connector
L1
L2
L3'
L4
L1'
L2'
L3
L4'
ICS557-06
Output
Clock
0.175 V
0.52 V
0.175 V
0.52 V
t
OR
t
OF
500 ps
500 ps
700 mV
0
MDS 557-06 C
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t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
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ICS557-06
One to Four HCSL Clock Buffer
LVDS Compatible Layout Guidelines
LVDS Device Routing
Typical LVDS Waveform
LVDS Recommendations for Differential Routing
Dimension or Value Unit
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
inch
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
R
P
100
ohm
R
Q
100
ohm
R
T
150
ohm
L3 length, Route as coupled 50 ohm differential trace.
L3 length, Route as coupled 50 ohm differential trace.
L1
L2'
L3
L1'
L2
L3'
R
Q
R
P
LVDS
Device
Load
ICS557-06
Clock
Output
R
T
R
T
1150 mV
1250 mV
t
OR
t
OF
500 ps
500 ps
1325 mV
1000 mV
1150 mV
1250 mV
MDS 557-06 C
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ICS557-06
One to Four HCSL Clock Buffer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-06. These ratings are
stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed
only over the recommended operating temperature range.
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70
C
1
Single edge is monotonic when transitioning through region.
2
Inputs with pull-ups/-downs are not included.
Item
Rating
Supply Voltage, VDD, VDDA
5.5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70
C
Storage Temperature
-65 to +150
C
Junction Temperature
125
C
Soldering Temperature
260
C
ESD Protection (Input)
2000 V min. (HBM)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Supply Voltage
V
3.135
3.465
Input High Voltage
1
V
IH
OE, SEL, PD
2.0
VDD +0.3
V
Input Low Voltage
1
V
IL
OE, SEL, PD
VSS-0.3
0.8
V
Input Leakage Current
2
I
IL
0 < Vin < VDD
-5
5
A
Operating Supply Current
I
DD
50
, 2pF
55
mA
I
DDOE
OE =Low
20
mA
I
DDPD
No load, PD =Low
400
A
Input Capacitance
C
IN
Input pin capacitance
7
pF
Output Capacitance
C
OUT
Output pin capacitance
6
pF
Pin Inductance
L
PIN
5
nH
Output Resistance
R
OUT
CLK outputs
3.0
k
Pull-up Resistor
R
PUP
SEL, OE, PD
110
k
MDS 557-06 C
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ICS557-06
One to Four HCSL Clock Buffer
AC Electrical Characteristics - CLKOUTA/CLKOUTB
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature 0 to +70
C
1
Test setup is R
L
=50 ohms with 2 pF, Rr = 475
(1%).
2
Measurement taken from a single-ended waveform.
3
Measurement taken from a differential waveform.
4
Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
5
CLKOUT pins are tri-stated when OE is Low asserted. CLKOUT is driven differential when OE is High unless its
PD = low.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
200
MHz
Output Frequency
HCSL termination
200
MHz
LVDS termination
100
Input High Voltage
1,2
V
IH
HCSL
660
700
850
mV
Input Low Voltage
1,2
V
IL
HCSL
-150
0
mV
Differential Input
Voltages
(V
ID
)
LVDS
250
350
450
mV
Input Offset Voltage
(V
IS
)
LVDS 1.125
1.25
1.375
V
Output High Voltage
1,2
V
OH
HCSL
660
700
850
mV
Output Low Voltage
1,2
V
OL
HCSL
-150
0
mV
Crossing Point
Voltage
1,2
Absolute
250
350
550
mV
Crossing Point
Voltage
1,2,4
Variation over all edges
140
mV
Jitter, Cycle-to-Cycle
1,3
100
ps
Rise Time
1,2
t
OR
From 0.175 V to 0.525 V
175
332
700
ps
Fall Time
1,2
t
OF
From 0.525 V to 0.175 V
175
344
700
ps
Rise/Fall Time
Variation
1,2
125
ps
Skew between Outputs
Measured at crossing point
50
ps
Duty Cycle
1,3
45
55
%
Output Enable Time
5
All outputs
10
us
Output Disable Time
5
All outputs
10
us
Stabilization Time
t
STABLE
From power-up VDD=3.3 V
3.0
ms
Spread Change Time
t
SPREAD
Settling period after spread change
3.0
ms
Input to Output Delay
Input differential clock to output
differential clock delay measured at
mid point of input levels to mid pint of
output levels
3
ns
MDS 557-06 C
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ICS557-06
One to Four HCSL Clock Buffer
Thermal Characteristics
Marking Diagram
Marking Diagram (Pb free)
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. "LF" denotes Pb free package.
4. Bottom marking: (origin). Origin = country of origin if not USA.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
93
C/W
JA
1 m/s air flow
78
C/W
JA
3 m/s air flow
65
C/W
Thermal Resistance Junction to Case
JC
20
C/W
10
20
11
######
YYWW
557G-06
ICS
1
10
20
11
######
YYWW
557G06LF
ICS
1
MDS 557-06 C
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w w w. i c s t . c o m
ICS557-06
One to Four HCSL Clock Buffer
Package Outline and Package Dimensions
(20-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS557G-06
See Page 4
Tubes
20-pin TSSOP
0 to +70
C
ICS557G-06T
Tape and Reel
20-pin TSSOP
0 to +70
C
ICS557G-06LF
Tubes
20-pin TSSOP
0 to +70
C
ICS557G-06LFT
Tape and Reel
20-pin TSSOP
0 to +70
C
INDEX
AREA
1 2
20
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa
C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters
Inches*
Symbol
Min
Max
Min
Max
A
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.0035
0.008
D
6.40
6.60
0.252
0.260
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
0
8
0
8
aaa
--
0.10
--
0.004
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