ICS557-03
MDS 557-03 E
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Description
The ICS557-03 is a spread spectrum clock generator
supporting PCI-Express and Ethernet requirements.
The device is used for PC or embedded systems to
substantially reduce electromagnetic interference
(EMI). The device provides two differential (HCSL)
spread spectrum outputs. This device is pin configured
to select spread and clock selection. Using ICS'
patented Phase-Locked Loop (PLL) techniques, the
device takes a 25 MHz crystal input and produces two
pairs of differential outputs (HCSL) at 25 MHz, 100
MHz, 125 MHz and 200 MHz clock frequencies. It also
provides spread selection of 0.25%, -0.5%, -0.75%,
and no spread.
Features
Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Supports LVDS Output Levels
Operating voltage of 3.3 V
Input frequency of 25 MHz
Outputs (HCSL, 0.7 V Current mode differential pair)
Jitter 100 ps (peak-to-peak)
Spread of 0.25%, -0.5%, -0.75%, and no spread.
Industrial and commercial temperature ranges
Block Diagram
Phase Lock Loop
Clock
Buffer/
Crystal
Oscillator
VDD
GND
X1/ICLK
X2
25 MHz
crystal or clock
Control
Logic
SS1:SS0
2
S1:S0
2
CLK0
CLK0
Rr(IREF)
CLK1
CLK1
2
2
OE
Optional tuning crystal
capacitors
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ICS557-03
Pin Assignment
Output Select Table 1(MHz)
Spread Selection Table 2
Pin Descriptions
1
2
3
X2
4
S1
5
6
CLK0
7
8
CLK0
GNDODA
VDDXD
OE
SS0
16
X1/ICLK
SS1
CLK1
VDDODA
15
14
13
12
11
10
9
16-pin (173 mil) TSSOP
GNDXD
S0
IREF
CLK1
S1
S0
CLK(1:0), CLK(1:0)
0
0
25M
0
1
100M
1
0
125M
1
1
200M
SS1
SS0
Spread %
0
0
Center 0.25
0
1
Down -0.5
1
0
Down -0.75
1
1
No Spread
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
S0
Input
Select pin 0. See Table1. Internal pull-up resistor.
2
S1
Input
Select pin 1. See Table 1. Internal pull-up resistor.
3
SS0
Input
Spread Select pin 0. See Table 2. Internal pull-up resistor.
4
X1/ICLK
Input
Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
5
X2
Output
Crystal connection. Leave unconnected for clock input.
6
OE
Input
Output enable tri-states outputs and device is not shut down. Internal
pull-up resistor.
7
GNDXD
Power
Connect to ground.
8
SS1
Input
Spread Select pin 1. See Table 2. Internal pull-up resistor.
9
IREF
Output
Precision resistor attached to this pin is connected to the internal current
reference.
10
CLK1
Output
HCSL compliment clock output.
11
CLK1
Output
HCSL clock output.
12
VDDODA
Power
Connect to voltage supply +3.3 V for output driver and analog circuits
13
GNDODA
Power
Connect to ground.
14
CLK0
Output
HCSL compliment clock output.
15
CLK0
Output
HCSL clock output.
16
VDDXD
Power
Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
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ICS557-03
Applications Information
External Components
A minimum number of external components are
required for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01
F should be connected
between each VDD pin and the ground plane, as close
to the VDD pin as possible. Do not share ground vias
between components. Route power from power source
through the capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300
ppm of error across temperature in order for the
ICS557-03 to meet PCI Express specifications.
Crystal Capacitors
Crystal capacitors are connected from pins X1 to
ground and X2 to ground to optimize the accuracy of
the output frequency.
C
L
= Crystal's load capacitance in pF
Crystal Capacitors (pF) = (C
L
- 8) * 2
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - R
R
If board target trace impedance (Z) is 50
, then R
R
=
475
(1%), providing IREF of 2.32 mA. The output
current (I
OH
) is equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-03 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the PCI-Express Layout Guidelines
section.
The ICS557-03 can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1. Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
2. No vias should be used between decoupling
capacitor and VDD pin.
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the ICS557-03.This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
R
R
475
6*IREF
=2.3 mA
IREF
See Output Termination
Sections - Pages 3 ~ 5
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ICS557-03
PCI-Express Layout Guidelines
PCI-Express Device Routing
Typical PCI-Express (HCSL)
Waveform
Common Recommendations for Differential Routing
Dimension or Value
Unit
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
inch
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
L3 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
R
S
33
ohm
R
T
49.9
ohm
Differential Routing on a Single PCB
Dimension or Value
Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
2 min to 16 max
inch
L4 length, Route as coupled stripline 100 ohm differential trace.
1.8 min to 14.4 max
inch
Differential Routing to a PCI Express Connector
Dimension or Value
Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
0.25 to 14 max
inch
L4 length, Route as coupled stripline 100 ohm differential trace.
0.225 min to 12.6 max inch
R
S
R
S
R
T
R
T
PCI-Express
Load or
Connector
L1
L2
L3'
L4
L1'
L2'
L3
L4'
ICS557-03
Output
Clock
0.175 V
0.52 V
0.175 V
0.52 V
t
OR
t
OF
500 ps
500 ps
700 mV
0
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ICS557-03
LVDS Compatible Layout Guidelines
LVDS Device Routing
Typical LVDS Waveform
LVDS Recommendations for Differential Routing
Dimension or Value Unit
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
inch
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
R
P
100
ohm
R
Q
100
ohm
R
T
150
ohm
L3 length, Route as coupled 50 ohm differential trace.
L3 length, Route as coupled 50 ohm differential trace.
L1
L2'
L3
L1'
L2
L3'
R
Q
R
P
LVDS
Device
Load
ICS557-03
Clock
Output
R
T
R
T
1150 mV
1250 mV
t
OR
t
OF
500 ps
500 ps
1325 mV
1000 mV
1150 mV
1250 mV
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ICS557-03
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-03. These ratings are
stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed
only over the recommended operating temperature range.
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85
C
1
Single edge is monotonic when transitioning through region.
2
Inputs with pull-ups/-downs are not included.
Item
Rating
Supply Voltage, VDD, VDDA
5.5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial)
0 to +70
C
Ambient Operating Temperature (industrial)
-40 to +85
C
Storage Temperature
-65 to +150
C
Junction Temperature
125
C
Soldering Temperature
260
C
ESD Protection (Input)
2000 V min. (HBM)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Supply Voltage
V
2.97
3.3
3.63
Input High Voltage
1
V
IH
S0, S1, OE, CLK, SS0, SS1
2.0
VDD +0.3
V
Input Low Voltage
1
V
IL
S0, S1, OE, CLK, SS0, SS1
VSS-0.3
0.8
V
Input Leakage Current
2
I
IL
0 < Vin < VDD
-5
5
A
Operating Supply Current
I
DD
50
, 2pF
65
mA
I
DDOE
OE =Low
35
mA
Input Capacitance
C
IN
Input pin capacitance
7
pF
Output Capacitance
C
OUT
Output pin capacitance
6
pF
Pin Inductance
L
PIN
5
nH
Output Resistance
R
OUT
CLKOUT
3.0
k
Pull-up Resistor
R
PU
100
k
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ICS557-03
AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1
Unless stated otherwise, VDD=3.3 V 10%, Ambient Temperature -40 to +85
C
Note 1: Test setup is R
L
=50 ohms with 2 pF, Rr = 475
(1%).
Note 2: Measurement taken from a single-ended waveform.
Note 3: Measurement taken from a differential waveform.
Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
25
MHz
Output Frequency
25
200
MHz
Output High Voltage
1,2
V
OH
Notes 1, 2
660
700
850
mV
Output Low Voltage
1,2
V
OL
Notes 1, 2
-150
0
mV
Crossing Point
Voltage
1,2
Absolute, Notes 1, 2
250
350
550
mV
Crossing Point
Voltage
1,2,4
Variation over all edges, Notes 1, 2, 4
140
mV
Jitter, Cycle-to-Cycle
1,3
Notes 1, 3
60
ps
Modulation Frequency
Spread spectrum
30
31.5
33
kHz
Rise Time
1,2
t
OR
From 0.175 V to 0.525 V, Notes 1, 2
175
332
700
ps
Fall Time
1,2
t
OF
From 0.525 V to 0.175 V, Notes 1, 2
175
344
700
ps
Rise/Fall Time
Variation
1,2
Notes 1, 2
125
ps
Skew between outputs
At VDD/2
50
ps
Duty Cycle
1,3
Notes 1, 3
45
55
%
Output Enable Time
5
All outputs, Note 5
10
us
Output Disable Time
5
All outputs, Note 5
10
us
Stabilization Time
t
STABLE
From power-up VDD=3.3 V
3.0
ms
Spread Change Time
t
SPREAD
Settling period after spread change
3.0
ms
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ICS557-03
Thermal Characteristics
Marking Diagram (ICS557G-03)
Marking Diagram (ICS557G-03LF)
Marking Diagram (ICS557GI-03)
Marking Diagram (ICS557GI-03LF)
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. "LF" designates Pb (lead) free package.
4. "I" deisgnates industrial temperature range.
5. Bottom marking: (origin). Origin = country of origin of not USA.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
78
C/W
JA
1 m/s air flow
70
C/W
JA
3 m/s air flow
68
C/W
Thermal Resistance Junction to Case
JC
37
C/W
8
16
9
######
YYWW
557G-03
ICS
1
8
16
9
######
YYWW
557G03LF
ICS
1
8
16
9
######
YYWW
557GI-03
ICS
1
8
16
9
######
YYWW
557GI03L
ICS
1
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ICS557-03
Package Outline and Package Dimensions
(16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS557G-03
See Page 8
Tubes
16-pin TSSOP
0 to +70
C
ICS557G-03T
Tape and Reel
16-pin TSSOP
0 to +70
C
ICS557G-03LF
Tubes
16-pin TSSOP
0 to +70
C
ICS557G-03LFT
Tape and Reel
16-pin TSSOP
0 to +70
C
ICS557GI-03
See Page 8
Tubes
16-pin TSSOP
-40 to +85
C
ICS557GI-03T
Tape and Reel
16-pin TSSOP
-40 to +85
C
ICS557GI-03LF
Tubes
16-pin TSSOP
-40 to +85
C
ICS557GI-03LFT
Tape and Reel
16-pin TSSOP
-40 to +85
C
INDEX
AREA
1 2
16
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.1
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
0
8
0
8
aaa
--
0.10
--
0.004
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