ICS558-02
MDS 558-02 D
1
Revision 020504
I n t e gra t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
LVHSTL
TO
CMOS C
LOCK
D
IVIDER
Description
The ICS558-02 accepts a high-speed LVHSTL input
and provides four CMOS low skew outputs from a
selectable internal divider (divide by 3, divide by 4). The
four outputs are split into two banks of two outputs.
Each bank has a separate output enable to tri-state the
output buffers.
The ICS558-02 is a member of the ICS Clock Blocks
TM
family of clock generation, synchronization, and
distribution devices.
Features
16-pin TSSOP package
LVHSTL inputs
Accepts up to 250 MHz input frequency
Four low skew (<250 ps) outputs
Selectable internal divider of 3 or 4
Operating voltage of 3.3 V
Block Diagram
OE1
CLK1
CLK2
CLK3
CLK4
HCLK
Output Divide
/3 or /4
HCLK
SEL
GND
VDD
OE0
4
3
LVHSTL
TO
CMOS C
LOCK
D
IVIDER
MDS 558-02 D
2
Revision 020504
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS558-02
Pin Assignment
Tri-State Table
Output Divide Selection
Pin Descriptions
12
1
11
2
10
3
9
SEL
4
VDD
5
VDD
6
VDD
7
HCLK
8
HCLK
CLK1
CLK2
CLK3
GND
CLK4
OE1
GND
GND
16
15
14
13
OE0
VDD
16 Pin 173 Mil (0.65mm) TSSOP
OE1
OE0
CLK 1, CLK 2
CLK 3, CLK 4
0
0
Tri-state
Tri-state
0
1
Clock ON
Tri-state
1
0
Tri-state
Clock ON
1
1
Clock ON
Clock ON
SEL
Output Divide
0
/3
1
/4
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
SEL
Input
Select pin for output divider. See table above. Internal pull-up to VDD.
2
VDD
Power
Connect to +3.3 V.
3
VDD
Power
Connect to +3.3 V.
4
HCLK
Input
Differential LVHSTL input (true input).
5
HCLK
Input
Differential LVHSTL input (complimentary input).
6
GND
Power
Connect to ground.
7
GND
Power
Connect to ground.
8
OE0
Input
Output enable for CLK1 and CLK2. See table above. Internal pull-up
to VDD.
9
OE1
Input
Output enable for CLK3 and CLK4. See table above. Internal pull-up
to VDD.
10
GND
Power
Connect to ground.
11
CLK4
Output
Low skew clock output.
12
CLK3
Output
Low skew clock output.
13
CLK2
Output
Low skew clock output.
14
CLK1
Output
Low skew clock output.
15
VDD
Power
Connect to +3.3 V.
16
VDD
Power
Connect to +3.3 V.
LVHSTL
TO
CMOS C
LOCK
D
IVIDER
MDS 558-02 D
3
Revision 020504
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS558-02
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS558-02. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
VDD=3.3 V 5%, Ambient temperature 0 to +70
C, unless stated otherwise stated.
Item
Rating
Supply Voltage
4.6 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
0 to +70
C
Storage Temperature
-65 to +150
C
Junction Temperature
125
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.15
+3.3
+3.5
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.135
3.3
3.465
V
Operating Supply Current
IDD
No load, 100 MHz
60
mA
Input High Voltage
V
IH
OE pins
VDD-0.5
VDD
V
Input Low Voltage
V
IL
OE pins
0.5
V
Input High Voltage
V
IH
HCLK
Vx + 0.1
1.2
V
Input Low Voltage
V
IL
HCLK
-0.3
Vx - 0.1
V
Peak to Peak Input Voltage
HCLK
0.3
1.0
V
HCLK Input Leakage
Current
I
IL
-20
20
A
Input Common Mode
Voltage
Vx
Input Common Mode
0.68
0.90
V
Output High Voltage
V
OH
I
OH
= -14.5 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 9.4 mA
0.4
V
LVHSTL
TO
CMOS C
LOCK
D
IVIDER
MDS 558-02 D
4
Revision 020504
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS558-02
AC Electrical Characteristics
VDD = 3.3 V 5%, Ambient Temperature 0 to +70
C, unless stated otherwise stated.
Thermal Characteristics (16-pin TSSOP)
Nominal Output Impedance
Z
O
20
Internal Pull-up Resistor
R
PU
250
k
Input Capacitance
C
IN
7
pF
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
0
250
MHz
Output Rise Time
t
OR
0.4 to 2.4 V, C
L
=30 pF
0.5
1.1
2.0
ns
Output Fall Time
t
OF
2.4 to 0.4 V, C
L
=30 pF
0.5
1.0
2.0
ns
Skew (between any two output
clocks)
30 pF load
0
250
ps
Propagation Delay
9
12
ns
Output Clock Duty Cycle
at VDD/2, C
L
=30 pF
45
50
55
%
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
78
C/W
JA
1 m/s air flow
70
C/W
JA
3 m/s air flow
68
C/W
Thermal Resistance Junction to Case
JC
37
C/W
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
LVHSTL
TO
CMOS C
LOCK
D
IVIDER
MDS 558-02 D
5
Revision 020504
I n t e gr a t e d C i r c u i t S y s t e m s
5 2 5 R a c e S t r e e t , S a n J o s e, C A 9 5 1 2 6
t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1
w w w. i c s t . c o m
ICS558-02
Package Outline and Package Dimensions
(16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit
Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of
third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice.
ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
Part / Order Number
Marking (both)
Shipping
packaging
Package
Temperature
ICS558G-02
ICS558G-02
Tubes
16-pin TSSOP
0 to 70
C
ICS558G-02T
ICS558G-02
Tape and Reel
16-pin TSSOP
0 to 70
C
INDEX
AREA
1 2
16
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.1
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
0
8
0
8
aaa
--
0.10
--
0.004
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