Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- AC Characteristics
- Additive Phase Jitter
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Propagation Delay Diagram
- Outupt Rise/Fall Time Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
ICS83115
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
83115BR
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 21, 2004
1
Integrated
Circuit
Systems, Inc.
G
ENERAL
D
ESCRIPTION
The ICS83115 is a low skew, 1-to-16 LVCMOS/
LVTTL Fanout Buffer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS83115 single ended
clock input accepts LVCMOS or LVTTL input lev-
els. The ICS83115 operates at full 3.3V supply mode over the
commercial temperature range. Guaranteed output and part-to-
part skew characteristics make the ICS83115 ideal for those
clock distribution applications demanding well defined perfor-
mance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
16 LVCMOS/LVTTL outputs
1 LVCMOS/LVTTL clock input
Maximum output frequency: 200MHz
All inputs are 5V tolerant
Output skew: 250ps (maximum)
Part-to-part skew: 800ps (maximum)
Additive phase jitter, RMS: 0.09ps (typical)
3.3V operating supply
0C to 70C ambient operating temperature
Lead-Free package available
Industrial temperature information available upon request
ICS83115
28-Lead SSOP, 150mil
9.9mm x 3.9mm x 1.7mm body package
R Package
(Top View)
HiPerClockSTM
ICS
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OE1
GND OE0
V
DD
IN
4
4
OE1
Q0
Q1
Q2
V
DD
V
DD
Q3
Q4
GND
GND
Q5
Q6
Q7
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE2
Q15
Q14
Q13
V
DD
V
DD
Q12
Q11
GND
GND
Q10
Q9
Q8
OE0
OE0
OE2
OE1
OE2
OE2
83115BR
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 21, 2004
2
ICS83115
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Integrated
Circuit
Systems, Inc.
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. F
UNCTION
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1
ICS83115
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
83115BR
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 21, 2004
3
Integrated
Circuit
Systems, Inc.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0
TO
70C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0
TO
70C
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/
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
49C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
83115BR
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 21, 2004
4
ICS83115
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Integrated
Circuit
Systems, Inc.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, T
A
= 0
TO
70C
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ICS83115
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
83115BR
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 21, 2004
5
Integrated
Circuit
Systems, Inc.
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter, RMS
@ 155.52MHz (12KHz to 20MHz)
= 0.09ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
83115BR
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 21, 2004
6
ICS83115
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Integrated
Circuit
Systems, Inc.
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
tsk(b)
V
DD
2
V
DD
2
Qy
Qx
tsk(pp)
V
DD
2
V
DD
2
Qy
Qx
Part 1
Part 2
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
t
PD
V
DD
2
V
DD
2
CLK
Q0:Q15
GND
V
DD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
Q0:Q15
ICS83115
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
83115BR
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 21, 2004
7
Integrated
Circuit
Systems, Inc.
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS83115 is: 985
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
28 L
EAD
SSOP, 150MIL
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
49C/W
36C/W
30C/W
NOTE: Most modern PCB designs use multi-layered boards.
83115BR
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 21, 2004
8
ICS83115
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Integrated
Circuit
Systems, Inc.
P
ACKAGE
O
UTLINE
- R S
UFFIX
FOR
28 L
EAD
SSOP, 150 MIL
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-137
L
O
B
M
Y
S
s
r
e
t
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i
l
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i
M
m
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x
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M
N
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2
A
5
3
.
1
5
7
.
1
1
A
0
1
.
0
5
2
.
0
2
A
0
5
.
1
b
0
2
.
0
0
3
.
0
c
8
1
.
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5
2
.
0
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.
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1
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.
6
1
E
0
8
.
3
0
0
.
4
e
C
I
S
A
B
5
3
6
.
0
L
0
4
.
0
7
2
.
1
0
8
D
Z
F
E
R
4
8
.
0
ICS83115
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
83115BR
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 21, 2004
9
Integrated
Circuit
Systems, Inc.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
T
ABLE
8. O
RDERING
I
NFORMATION
r
e
b
m
u
N
r
e
d
r
O
/
t
r
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R
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C
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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