Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Output Enable and Clock Enable Function Table
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 2.5V DC Characteristics
- Power Supply 1.8V DC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- Power Supply 3.3V/1.8V DC Characteristics
- Power Supply 2.5V/1.8V DC Characteristics
- LVCMOS DC Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- 1.8V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 3.3V/1.8V AC Characteristics
- 2,5V/1.8V AC Characteristics
- Parameter Measurement Information
- 3.3V Core/3.3V Output Load AC Test Circuit Diagram
- 2.5V Core/2.5V Output Load AC Test Circuit Diagram
- 1.8V Core/1.8V Output Load AC Test Circuit Diagram
- 3.3V Core/2.5V Output Load AC Test Circuit Diagram
- 3.3V Core/1.8V Output Load AC Test Circuit Diagram
- 2.5V Core/1.8V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
8312AYI
http://www.icst.com/products/hiperclocks.html
REV. A OCTOBER 23, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8312I is a low skew, 1-to-12 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS8312I single ended
clock input accepts LVCMOS or LVTTL input lev-
els. The low impedance LVCMOS outputs are designed to
drive 50
series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
The ICS8312I is characterized at full 3.3V, 2.5V, and 1.8V, or
mixed 3.3V core/2.5V, 3.3V core/1.8V and 2.5V core/1.8V out-
put operating supply modes. Guaranteed output and part-to-
part skew characteristics along with the 1.8V output capa-
bilities makes the ICS8312I ideal for high performance, single
ended applications that also require a limited output voltage.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
12 LVCMOS / LVTTL outputs
LVCMOS / LVTTL clock input
Maximum output frequency: 250MHz
Output skew: 160ps (maximum)
Operating supply modes: Core/Output
3.3V/3.3V
2.5V/2.5V
1.8V/1.8V
3.3V/2.5V
3.3V/1.8V
2.5V/1.8V
-40C to 85C ambient operating temperature
HiPerClockSTM
ICS
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
GND
GND
V
DD
CLK_EN
CLK
GND
OE
V
DD
GND
GND
Q8
V
DDO
Q9
GND
Q10
V
DDO
Q11
GND
Q3
V
DDO
Q2
GND
Q1
V
DDO
Q0
ICS8312I
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Pacakge
Top View
Q0:Q11
CLK_EN
CLK
OE
nD
Q
LE
12
8312AYI
http://www.icst.com/products/hiperclocks.html
REV. A OCTOBER 23, 2003
2
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3A. O
UTPUT
E
NABLE
AND
C
LOCK
E
NABLE
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
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8312AYI
http://www.icst.com/products/hiperclocks.html
REV. A OCTOBER 23, 2003
3
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
l
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A
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
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A
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
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A
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
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0
1
A
T
ABLE
4E. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
l
o
b
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0
1
A
T
ABLE
4F. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
l
o
b
m
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S
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2
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2
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2
6
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2
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0
1
A
8312AYI
http://www.icst.com/products/hiperclocks.html
REV. A OCTOBER 23, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
4F. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
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g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
K
L
C
V
D
D
%
5
V
3
.
3
=
2
V
D
D
3
.
0
+
V
V
D
D
%
5
V
5
.
2
=
7
.
1
V
D
D
3
.
0
+
V
V
D
D
V
2
.
0
V
8
.
1
=
V
*
5
6
.
0
D
D
V
D
D
3
.
0
+
V
E
O
,
N
E
_
K
L
C
V
D
D
%
5
V
3
.
3
=
2
V
D
D
3
.
0
+
V
V
D
D
%
5
V
5
.
2
=
7
.
1
V
D
D
3
.
0
+
V
V
D
D
V
2
.
0
V
8
.
1
=
V
*
5
6
.
0
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D
V
D
D
3
.
0
+
V
V
L
I
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g
a
t
l
o
V
w
o
L
t
u
p
n
I
K
L
C
V
D
D
%
5
V
3
.
3
=
3
.
0
-
3
.
1
V
V
D
D
%
5
V
5
.
2
=
3
.
0
-
7
.
0
V
V
D
D
V
2
.
0
V
8
.
1
=
3
.
0
-
V
*
5
3
.
0
D
D
V
E
O
,
N
E
_
K
L
C
V
D
D
%
5
V
3
.
3
=
3
.
0
-
3
.
1
V
V
D
D
%
5
V
5
.
2
=
3
.
0
-
7
.
0
V
V
D
D
V
2
.
0
V
8
.
1
=
3
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0
-
V
*
5
3
.
0
D
D
V
I
H
I
t
n
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r
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C
h
g
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H
t
u
p
n
I
K
L
C
V
D
D
%
5
V
3
.
3
=
0
5
1
A
V
D
D
%
5
V
5
.
2
=
0
5
1
A
V
D
D
V
2
.
0
V
8
.
1
=
0
5
1
A
E
O
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N
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K
L
C
V
D
D
%
5
V
3
.
3
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5
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V
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D
%
5
V
5
.
2
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5
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V
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D
V
2
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0
V
8
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1
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I
L
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w
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D
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5
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3
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A
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D
%
5
V
5
.
2
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5
-
A
V
D
D
V
2
.
0
V
8
.
1
=
5
-
A
E
O
,
N
E
_
K
L
C
V
D
D
%
5
V
3
.
3
=
0
5
1
-
A
V
D
D
%
5
V
5
.
2
=
0
5
1
-
A
V
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D
V
2
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0
V
8
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1
=
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5
1
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g
a
t
l
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h
g
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H
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u
p
t
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V
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D
D
1
E
T
O
N
;
%
5
V
3
.
3
=
6
.
2
V
V
O
D
D
I
;
%
5
V
5
.
2
=
H
O
A
m
1
-
=
2
V
V
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D
D
1
E
T
O
N
;
%
5
V
5
.
2
=
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.
1
V
V
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D
D
I
;
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2
.
0
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8
.
1
=
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A
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0
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=
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D
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.
0
-
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V
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D
D
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T
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N
;
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0
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1
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D
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5
V
3
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3
=
5
.
0
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V
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D
D
I
;
%
5
V
5
.
2
=
L
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m
1
=
4
.
0
V
V
O
D
D
1
E
T
O
N
;
%
5
V
5
.
2
=
5
4
.
0
V
V
O
D
D
I
;
V
2
.
0
V
8
.
1
=
L
O
A
u
0
0
1
=
2
.
0
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V
O
D
D
1
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T
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N
;
V
2
.
0
V
8
.
1
=
5
3
.
0
V
0
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h
t
i
w
d
e
t
a
n
i
m
r
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t
s
t
u
p
t
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:
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.
s
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t
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m
a
r
a
P
e
e
S
.
2
/
8312AYI
http://www.icst.com/products/hiperclocks.html
REV. A OCTOBER 23, 2003
5
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
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m
a
r
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P
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n
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t
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T
m
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L
1
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;
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g
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w
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b
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C
5
e
l
b
a
T
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S
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 1.8V0.2V, T
A
= -40C
TO
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l
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m
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1
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4
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k
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0
6
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k
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,
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;
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t
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4
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m
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2
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3
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5
6
d
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m
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h
T
:
5
E
T
O
N
8312AYI
http://www.icst.com/products/hiperclocks.html
REV. A OCTOBER 23, 2003
6
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
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UFFER
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8312AYI
http://www.icst.com/products/hiperclocks.html
REV. A OCTOBER 23, 2003
7
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
1.8V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.40.9V
V
DDO
-0.9V0.1V
V
DD
0.9V0.1V
SCOPE
Qx
LVCMOS
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.05V5%
V
DDO
-1.25V5%
V
DD
1.25V5%
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.165V5%
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5 C
ORE
/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
SCOPE
Qx
LVCMOS
0.9V 0.1V
-0.9V 0.1V
SCOPE
Qx
LVCMOS
2.05V5%
V
DDO
-0.9V0.1V
V
DD
0.9V0.1V
V
DD
,
V
DDO
GND
V
DD
,
V
DDO
GND
V
DD
,
V
DDO
GND
GND
GND
GND
8312AYI
http://www.icst.com/products/hiperclocks.html
REV. A OCTOBER 23, 2003
8
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
Q0:Q11
t
PD
V
DD
2
V
DDO
2
CLK
Q0:Q11
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
S
KEW
P
ROPAGATION
D
ELAY
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
tsk(o)
V
DDO
2
V
DDO
2
Qy
Qx
tsk(pp)
V
DDO
2
V
DDO
2
Qy
Qx
Part 1
Part 2
8312AYI
http://www.icst.com/products/hiperclocks.html
REV. A OCTOBER 23, 2003
9
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8312I is: 339
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8312AYI
http://www.icst.com/products/hiperclocks.html
REV. A OCTOBER 23, 2003
10
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
Reference Document: JEDEC Publication 95, MS-026
8312AYI
http://www.icst.com/products/hiperclocks.html
REV. A OCTOBER 23, 2003
11
Integrated
Circuit
Systems, Inc.
ICS8312I
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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