Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Output Enable & Clock Enable Function Table
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- Application Information
- Recommendations for Unused Input and Output Pins
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
8316AK
http://www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2005
1
Integrated
Circuit
Systems, Inc.
ICS8316
L
OW
S
KEW
, 1-
TO
-16, LVCMOS / LVTTL
F
ANOUT
B
UFFER
W
/1.2V LVCMOS O
UTPUTS
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS8316 is a low skew, 1-to-16 LVCMOS/
LVTTL Fanout Buffer with 1.2V LVCMOS Outputs
and a member of the HiPerClockSTM family of
High Performance Clock Solutions from ICS. The
ICS8316 single ended clock input accepts
LVCMOS or LVTTL input levels. The low impedance LVCMOS
outputs are designed to drive 50
series or parallel termi-
nated transmission lines.
Guaranteed output and part-to-part skew characteristics
along with the 1.2V output makes the ICS8316 ideal for high
performance, single ended applications that also require a
limited output voltage.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Sixteen 1.2V LVCMOS / LVTTL outputs
LVCMOS / LVTTL clock input
Maximum output frequency: 150MHz
Output skew: TBD
Propagation delay: 3.5ns (typical)
3.3V core/1.2V output operating supply mode
0C to 70C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free RoHS-compliant
packages
HiPerClockSTM
ICS
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
DDO
QC0
QC1
QC2
QC3
GND
OEC
GND
V
DDO
QA0
QA1
QA2
QA3
GND
OEA
CLK
ICS8316
32-Lead VFQFN
5mm x 5mm x 0.95 package body
K Package
Top View
QA0:QA3
CLK
OEA
OEB
OEC
OED
V
DD
OEB
GND
QB3
QB2
QB1
QB0
V
DDO
GND
OED
GND
QD3
QD2
QD1
QD0
V
DDO
4
4
4
4
QB0:QB3
QC0:QC3
QD0:QD3
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
8316AK
http://www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2005
2
Integrated
Circuit
Systems, Inc.
ICS8316
L
OW
S
KEW
, 1-
TO
-16, LVCMOS / LVTTL
F
ANOUT
B
UFFER
W
/1.2V LVCMOS O
UTPUTS
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3A. O
UTPUT
E
NABLE
AND
C
LOCK
E
NABLE
F
UNCTION
T
ABLE
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ABLE
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LOCK
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NPUT
F
UNCTION
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A
8316AK
http://www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2005
3
Integrated
Circuit
Systems, Inc.
ICS8316
L
OW
S
KEW
, 1-
TO
-16, LVCMOS / LVTTL
F
ANOUT
B
UFFER
W
/1.2V LVCMOS O
UTPUTS
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V, V
DDO
= 1.2V5%, T
A
= 0C
TO
70C
l
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b
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
34.8C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
T
A
= 0C
TO
70C
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1
=
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0
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5
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.
1
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3
.
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T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 1.2V5%, T
A
= 0C
TO
70C
l
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8316AK
http://www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2005
4
Integrated
Circuit
Systems, Inc.
ICS8316
L
OW
S
KEW
, 1-
TO
-16, LVCMOS / LVTTL
F
ANOUT
B
UFFER
W
/1.2V LVCMOS O
UTPUTS
PRELIMINARY
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
t
PD
V
DD
2
V
DDO
2
CLK
QA0:QA3,
QB0:QB3,
QC0:QC3,
QD0:QD3
O
UTPUT
R
ISE
/F
ALL
T
IME
QA0:QA3,
QB0:QB3,
QC0:QC3,
QD0:QD3
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
2.7V5%
V
DDO
-0.6V5%
V
DD
0.6V5%
P
ART
-
TO
-P
ART
S
KEW
GND
O
UTPUT
D
UTY
C
YCLE
/P
LUSE
W
IDTH
/P
ERIOD
P
ROPAGATION
D
ELAY
t
sk(o)
V
DDO
2
V
DDO
2
Qy
Qx
t
sk(pp)
V
DDO
2
V
DDO
2
Qy
Qx
Part 1
Part 2
B
ANK
S
KEW
(
where x denotes outputs in the same bank
)
t
sk(b)
V
DDO
2
V
DDO
2
Qx0:Qx3
Qx0:Qx3
O
UTPUT
S
KEW
3.3V C
ORE
/1.2V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
8316AK
http://www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2005
5
Integrated
Circuit
Systems, Inc.
ICS8316
L
OW
S
KEW
, 1-
TO
-16, LVCMOS / LVTTL
F
ANOUT
B
UFFER
W
/1.2V LVCMOS O
UTPUTS
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8316 is: 416
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
VFQFN
JA
vs. 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8C/W
A
PPLICATION
I
NFORMATION
I
NPUTS
:
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
8316AK
http://www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2005
6
Integrated
Circuit
Systems, Inc.
ICS8316
L
OW
S
KEW
, 1-
TO
-16, LVCMOS / LVTTL
F
ANOUT
B
UFFER
W
/1.2V LVCMOS O
UTPUTS
PRELIMINARY
T
ABLE
7. P
ACKAGE
D
IMENSIONS
P
ACKAGE
O
UTLINE
AND
D
IMENSIONS
- K S
UFFIX
FOR
32 L
EAD
VFQFN
Reference Document: JEDEC Publication 95, MO-220
N
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.
0
8316AK
http://www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2005
7
Integrated
Circuit
Systems, Inc.
ICS8316
L
OW
S
KEW
, 1-
TO
-16, LVCMOS / LVTTL
F
ANOUT
B
UFFER
W
/1.2V LVCMOS O
UTPUTS
PRELIMINARY
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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