Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- LVCMOS 3.3V DC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- LVCMOS 3.3V/2.5V DC Characterisitcs
- Power Supply 2.5V DC Characteristics
- LVCMOS 2.5V DC Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 2.5V AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 3.3V/2.5V Output Load AC Test Circuit Diagram
- 2.5V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- Part-to-Part Skew Diagram
- Output Rise/Fall Time Diagram
- Propagation Delay Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
8343AYI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 22, 2004
1
Integrated
Circuit
Systems, Inc.
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS8343I-01 is a low skew, 1-to-16
LVCMOS/LVTTL Fanout Buffer and a member of
the HiPerClockSTM family of High Performance
Clock Solutions from ICS. The ICS8343I-01
single ended clock input accepts LVCMOS or
LVTTL input levels. The ICS8343I-01 operates at 3.3V,
2.5V and mixed 3.3V input and 2.5V supply modes over the
commercial temperature range. Guaranteed output and part-
to-part skew characteristics make the ICS8343I-01 ideal for
those clock distribution applications demanding well defined
performance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
16 LVCMOS/LVTTL outputs
1 LVCMOS/LVTTL clock input
CLK can accept the following input levels: LVCMOS, LVTTL
Maximum output frequency: 200MHz
Dual output enable inputs facilitates 1-to-16 or 1-to-8 input
to output modes
All inputs are 5V tolerant
Output skew: 250ps (typical)
Part-to-part skew: 700ps (typical)
Full 3.3V and 2.5V or mixed 3.3V core/2.5V operating supply
-40C to 85C ambient operating temperature
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
DD
2
V
DD
2
V
DD
2
Q12
Q11
GND
GND
GND
V
DD
1
V
DD
1
V
DD
1
Q3
Q4
GND
GND
GND
Q10
Q9
Q8
V
DD
CLK
Q7
Q6
Q5
Q13
Q14
Q15
OE2
OE1
Q0
Q1
Q2
ICS8343I-01
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
(Top View)
HiPerClockSTM
ICS
CLK
OE2
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
OE1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
VDD1
VDD2
VDD
GND
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OE1
GND
OE2
V
DD1
V
DD
V
DD2
CLK
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8343AYI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 22, 2004
2
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Integrated
Circuit
Systems, Inc.
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. F
UNCTION
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ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
8343AYI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 22, 2004
3
Integrated
Circuit
Systems, Inc.
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 3.3V5%, T
A
= -40
TO
85C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 3.3V5%, T
A
= -40
TO
85C
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/
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDx
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8343AYI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 22, 2004
4
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Integrated
Circuit
Systems, Inc.
PRELIMINARY
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DD1
= V
DD2
= 2.5V5%, T
A
= -40
TO
85C
T
ABLE
4D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DD1
= V
DD2
= 2.5V5%, T
A
= -40
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
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C
t
s
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T
m
u
m
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M
l
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p
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x
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5
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1
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3
5
6
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.
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V
V
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D
D
1
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T
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;
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5
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3
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5
.
2
/
V
3
.
3
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
8343AYI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 22, 2004
5
Integrated
Circuit
Systems, Inc.
PRELIMINARY
T
ABLE
4F. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 2.5V5%, T
A
= -40
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
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T
m
u
m
i
x
a
M
s
t
i
n
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V
H
I
e
g
a
t
l
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V
h
g
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H
t
u
p
n
I
2
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O
,
1
E
O
2
V
D
D
3
.
0
+
V
K
L
C
2
V
D
D
3
.
0
+
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V
L
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p
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w
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2
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1
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D
D
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=
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5
2
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2
=
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K
L
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D
D
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=
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2
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S
.
2
/
T
ABLE
4E. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 2.5V5%, T
A
= -40
TO
85C
l
o
b
m
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S
r
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.
8343AYI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 22, 2004
6
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Integrated
Circuit
Systems, Inc.
PRELIMINARY
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= V
DD1
= V
DD2
= 2.5V5%, T
A
= -40
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
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ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
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= V
DD2
= 3.3V5%, T
A
= -40
TO
85C
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ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
8343AYI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 22, 2004
7
Integrated
Circuit
Systems, Inc.
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
2.05V5%
V
DDx
-1.25V5%
V
DD
1.25V5%
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5V C
ORE
/ 2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/ 3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
tsk(o)
V
DDx
2
V
DDx
2
Qy
Qx
tsk(pp)
V
DDx
2
V
DDx
2
Qy
Qx
Part 1
Part 2
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
DD
,
V
DDx
GND
GND
V
DD
,
V
DDx
GND
8343AYI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 22, 2004
8
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Integrated
Circuit
Systems, Inc.
PRELIMINARY
P
ROPAGATION
D
ELAY
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
PD
V
DDx
2
V
DDx
2
CLK
Q0:Q15
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDx
2
Q0:Q15
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
8343AYI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 22, 2004
9
Integrated
Circuit
Systems, Inc.
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8343I-01 is: 985
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8343AYI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 22, 2004
10
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
Integrated
Circuit
Systems, Inc.
PRELIMINARY
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
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M
I
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N
I
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N
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N
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M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
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M
L
A
N
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O
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X
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M
N
2
3
A
-
-
-
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0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
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2
.
0
D
C
I
S
A
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0
0
.
9
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A
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0
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.
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0
6
.
5
E
C
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S
A
B
0
0
.
9
1
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C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
ICS8343I-01
L
OW
S
KEW
, 1-
TO
-16
LVCMOS / LVTTL F
ANOUT
B
UFFER
8343AYI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 22, 2004
11
Integrated
Circuit
Systems, Inc.
PRELIMINARY
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
T
ABLE
8. O
RDERING
I
NFORMATION
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
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k
c
a
P
t
n
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o
C
e
r
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t
a
r
e
p
m
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T
1
0
-
I
Y
A
3
4
3
8
S
C
I
1
0
-
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Y
A
3
4
3
8
S
C
I
P
F
Q
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2
3
y
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p
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2
C
5
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t
C
0
4
-
T
1
0
-
I
Y
A
3
4
3
8
S
C
I
1
0
-
I
Y
A
3
4
3
8
S
C
I
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R
d
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p
a
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P
F
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L
d
a
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L
2
3
0
0
0
1
C
5
8
o
t
C
0
4
-
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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