8344AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 6, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8344-01 is a low voltage, low skew
fanout buffer and a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS. The ICS8344-01 has two selectable clock
inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs
can accept most standard differential input levels. The
ICS8344-01 is designed to translate any differential signal
levels to LVCMOS levels. The low impedance LVCMOS out-
puts are designed to drive 50
series or parallel terminated
transmission lines. The effective fanout can be increased to
48 by utilizing the ability of the outputs to drive two series
terminated lines. Redundant clock applications can make use
of the dual clock input. The dual clock inputs also facilitate
board level testing. The clock enable is internally synchro-
nized to eliminate runt pulses on the outputs during asyn-
chronous assertion/deassertion of the clock enable pin. The
outputs are driven low when disabled. The ICS8344-01 is
characterized at full 3.3V, full 2.5V and mixed 3.3V input and
2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS8344-01 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
F
EATURES
24 LVCMOS outputs, 7
typical output impedance
2 selectable CLKx, nCLKx inputs
CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following input levels: LVDS, LVPECL, LVHSTL, SSTL,
HCSL
Output frequency up to 250MHz
Translates any single ended input signal to LVCMOS with
resistor bias on nCLK input
Synchronous clock enable
Output skew: 200 ps (maximum)
Part-to-part skew: 900ps (maximum)
Bank skew: 85ps (maximum)
Propagation delay: 5ns (maximum)
3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
HiPerClockSTM
,&6
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Q16
Q17
V
DDO
GND
Q18
Q19
Q20
Q21
V
DDO
GND
Q22
Q23
Q7
Q6
V
DDO
GND
Q5
Q4
Q3
Q2
V
DDO
GND
Q1
Q0
nc
OE
CLK_EN
CLK0
nCLK0
V
DD
GND
CLK1
nCLK1
V
DD
GND
CLK_SEL
Q8
Q9
V
DDO
GND
Q10
Q11
Q12
Q13
V
DDO
GND
Q14
Q15
48-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
ICS8344-01
Q0 - Q7
Q8 - Q15
Q16 - Q23
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_EN
OE
LE
Q
nD
1
0
8344AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 6, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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8344AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 6, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
3A. O
UPUT
E
NABLE
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
T
ABLE
3C. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
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8344AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 6, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
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u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
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S
e
v
i
t
i
s
o
P
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
D
D
e
g
a
t
l
o
V
y
l
p
p
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O
5
3
1
.
3
3
.
3
5
6
4
.
3
V
I
D
D
t
n
e
r
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u
C
y
l
p
p
u
S
r
e
w
o
P
t
n
e
c
s
e
i
u
Q
5
9
A
m
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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t
e
m
a
r
a
P
s
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T
m
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l
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m
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U
I
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I
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n
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r
r
u
C
h
g
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H
t
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p
n
I
1
K
L
C
n
,
0
K
L
C
n
V
D
D
V
=
N
I
V
5
6
4
.
3
=
5
A
1
K
L
C
,
0
K
L
C
V
D
D
V
=
N
I
V
5
6
4
.
3
=
0
5
1
A
I
L
I
t
n
e
r
r
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C
w
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n
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1
K
L
C
n
,
0
K
L
C
n
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
1
K
L
C
,
0
K
L
C
V
D
D
V
,
V
5
6
4
.
3
=
N
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0
=
5
-
A
V
P
P
e
g
a
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l
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e
P
3
.
0
3
.
1
V
V
R
M
C
2
,
1
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T
O
N
:
e
g
a
t
l
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V
t
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p
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d
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M
n
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m
m
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C
9
.
0
2
V
V
s
i
1
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L
C
n
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1
K
L
C
d
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a
0
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L
C
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,
0
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L
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f
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g
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il
p
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g
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F
:
1
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T
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D
D
.
V
3
.
0
+
V
s
a
d
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n
i
f
e
d
s
i
e
g
a
t
l
o
v
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d
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m
n
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m
m
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C
:
2
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T
O
N
H
I
.
l
o
b
m
y
S
r
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e
m
a
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P
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C
t
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T
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2
8
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3
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V
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a
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l
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w
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3
.
0
-
8
.
0
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g
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,
N
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_
K
L
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V
D
D
V
=
N
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V
5
6
4
.
3
=
5
A
L
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S
_
K
L
C
V
D
D
V
=
N
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5
6
4
.
3
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1
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E
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K
L
C
V
D
D
V
,
5
6
4
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3
=
N
I
V
0
=
0
5
1
-
A
L
E
S
_
K
L
C
V
D
D
V
,
5
6
4
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3
=
N
I
V
0
=
5
-
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V
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O
e
g
a
t
l
o
V
h
g
i
H
t
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p
t
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V
D
D
V
=
O
D
D
V
5
3
1
.
3
=
I
H
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m
6
3
-
=
7
.
2
V
V
L
O
e
g
a
t
l
o
V
w
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L
t
u
p
t
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V
D
D
V
=
O
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V
5
3
1
.
3
=
I
L
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A
m
6
3
=
5
.
0
V
8344AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 6, 2001
5
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
4F. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4E. LVCMOS DC C
HARACTERISTICS
,
VDDI = V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
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l
o
V
y
l
p
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e
v
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t
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o
P
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
D
D
e
g
a
t
l
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V
y
l
p
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O
5
7
3
.
2
5
.
2
5
2
6
.
2
V
I
D
D
t
n
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r
r
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C
y
l
p
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r
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w
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P
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c
s
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5
9
A
m
l
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m
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m
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T
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V
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g
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I
,
N
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K
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C
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2
8
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3
V
V
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a
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l
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w
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I
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3
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0
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5
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3
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5
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L
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3
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5
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3
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9
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1
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3
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2
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4
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l
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0
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L
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V
D
D
V
=
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5
6
4
.
3
=
5
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1
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0
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L
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V
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D
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5
6
4
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3
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0
5
1
A
I
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r
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1
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5
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4
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3
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L
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5
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3
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g
a
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l
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9
.
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V
s
i
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L
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n
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L
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d
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a
0
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L
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,
0
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L
C
r
o
f
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g
a
t
l
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m
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m
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p
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D
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3
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s
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m
m
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:
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I
.
8344AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 6, 2001
6
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
4H. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4I. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
T
ABLE
4G. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
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n
i
M
l
a
c
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p
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T
m
u
m
i
x
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M
s
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n
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V
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5
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I
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C
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w
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5
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A
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1
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n
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L
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V
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D
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=
N
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5
2
6
.
2
=
5
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1
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0
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L
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2
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1
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5
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:
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V
8344AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 6, 2001
7
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%; V
DD
= 3.3V 5%, V
DDO
= 2.5V 5%;
V
DD
= V
DDO
= 2.5V 5%, T
A
= 0C
TO
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N
8344AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 6, 2001
8
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
F
IGURE
1A - 3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DD
= +1.65V
V
DDO
= 1.65V
V
DD
GND = -1.65V
V
DDO
F
IGURE
1B - 2.5V O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DDO
= +1.25V
V
DDO
GND = -1.25V
8344AY-01
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REV. B AUGUST 6, 2001
9
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
F
IGURE
3 - O
UTPUT
S
KEW
tsk(o)
Qx
Qy
F
IGURE
4 - P
ART
-
TO
-P
ART
S
KEW
Qx
Qy
PART 1
PART 2
tsk(pp)
F
IGURE
2 - D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
CLK0, CLK 1
nCLK0, nCLK1
GND
V
DD
8344AY-01
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REV. B AUGUST 6, 2001
10
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
F
IGURE
5 - I
NPUT
AND
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Inputs
and Outputs
30%
70%
30%
70%
trise
tfall
V
S W I N G
F
IGURE
6 - P
ROPAGATION
D
ELAY
t
PD
CLK0, CLK1
Q0 - Q23
F
IGURE
7 - odc & t
P
ERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
CLK0, CLK1,
Q0 - Q23
nCLK0, nCLK1
nCLK0, nCLK1
8344AY-01
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REV. B AUGUST 6, 2001
11
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
F
IGURE
8 - S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
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REV. B AUGUST 6, 2001
12
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8344-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8344-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 95mA = 329.2mW
Power (outputs)
MAX
= 32mW/Loaded Output pair
If all outputs are loaded, the total power is 24* 32mW = 768mW
Total Power
_MAX
(3.465V, with all outputs switching) = 329.2mW + 768mW = 1097.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.1097W * 42.1C/W = 74.6C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 6. Thermal Resistance
q
JA
for 48-pin LQFP, Forced Convection
8344AY-01
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REV. B AUGUST 6, 2001
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Integrated
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ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVCMOS output driver circuit and termination are shown in
Figure 9.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
DD
- 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R
L
) * (V
DD_MAX
- V
OH_MAX
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DD_MAX
- V
OL_MAX
)
For logic high, V
OUT
= V
OH_MAX
= V
DD_MAX
1.2V
For logic low, V
OUT
= V
OL_MAX
= V
DD_MAX
0.4V
Pd_H = (1.2V/50
) * (2V - 1.2V) = 19.2mW
Pd_L = (0.4V/50
) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
F
IGURE
9 - LVCMOS D
RIVER
C
IRCUIT
AND
T
ERMINATION
V
DDO
V
OUT
RL
50
Q1
8344AY-01
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REV. B AUGUST 6, 2001
14
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8344-01 is: 1503
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8344AY-01
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REV. B AUGUST 6, 2001
15
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
N
O
I
T
A
I
R
A
V
C
E
D
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J
S
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T
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M
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A
L
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B
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P
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O
UTLINE
- Y S
UFFIX
T
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8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
8344AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 6, 2001
16
Integrated
Circuit
Systems, Inc.
ICS8344-01
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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