Document Outline
- General Description
- Features
- Simplified Schematic
- Logic Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- DC Characteristics
- AC Characteristics
- Parameter Measurement Information
- 2.5V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- Bank Skew Diagram
- 3-State Output enable/Disable Times Diagram
- Propagation Delay Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
83840AH
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2003
1
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
G
ENERAL
D
ESCRIPTION
The ICS83840 is a DDR SDRAM MUX and is
a member of the HiPerClock STM family of High
Performance Clock Solutions from ICS. The
device has 10 Host Lines and each host line can
be passed to 4 Data Ports. The 10 channels are
allocated as follows in the DDR SDRAM application: 8 data
lines, 1 strobe line and 1 DQm line. The Host/Data Ports are
compatible with single-ended SSTL-2 and the device oper-
ates from a 2.5V supply.
Guaranteed low output skew makes the ICS83840 ideal for
demanding applications which require well defined perfor-
mance and repeatability.
L
OGIC
D
IAGRAM
F
EATURES
40 low skew single-ended DIMM ports
4 SSTL-2 compatible enable inputs
Maximum Switching Speed: 3ns
Output skew: 120ps (maximum)
Bank skew: 45ps (maximum)
r
on
= 8
(typical)
Full 2.5V supply modes
0C to 70C ambient operating temperature
Pin compatible with the CBTV4010
HiPerClockSTM
ICS
S
IMPLIFIED
S
CHEMATIC
HPx
nSn
nDPx
SW
400
HP0
0DP0
1DP0
2DP0
3DP0
HP9
Sw
Sw
Sw
Sw
0DP9
1DP9
2DP9
3DP9
Sw
Sw
Sw
Sw
nS0
nS1
nS2
nS3
R
ON
R
ON
ICS83840
64-Ball TFBGA
7mm x 7mm x 1.2mm
package body
H Package
Top View
P
IN
A
SSIGNMENT
V
D
D
1
S
n
c
n
0
P
D
1
0
P
D
2
0
P
D
3
1
P
D
2
1
P
D
3
2
P
D
0
2
S
n
V
D
D
0
S
n
D
N
G
0
P
D
0
0
P
H
1
P
D
0
1
P
D
1
1
P
H
D
N
G
2
P
D
1
c
n
3
S
n
2
P
H
2
P
D
2
D
N
G
2
P
D
3
9
P
D
2
9
P
D
3
3
P
D
0
3
P
D
1
9
P
D
1
9
P
H
3
P
H
3
P
D
2
9
P
D
0
8
P
D
3
D
N
G
3
P
D
3
8
P
D
2
4
P
D
0
8
P
D
1
8
P
H
4
P
H
4
P
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1
8
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0
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7
P
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7
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0
6
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1
6
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6
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1
6
P
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0
5
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D
2
5
P
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1
5
P
D
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1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
83840AH
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2003
2
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
T
ABLE
1. P
IN
D
ESCRIPTIONS
r
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ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. F
UNCTION
T
ABLE
t
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F
p
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:
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T
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N
83840AH
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2003
3
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V 0.2V, T
A
= 0C
TO
70C
l
o
b
m
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S
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0
5
A
T
ABLE
4B. DC C
HARACTERISTICS
,
V
DD
= 2.5V 0.2V, T
A
= 0C
TO
70C
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5
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2
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;
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2
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V
;
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8
.
0
=
B
V
0
.
1
=
5
8
3
1
V
D
D
V
;
V
5
.
2
=
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V
;
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7
.
1
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h
c
t
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w
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t
f
o
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
-0.5V to +3.3V
Inputs, V
I
-0.3V to V
DD
+ 0.3 V
Ports
DC Input Clamp Current, I
IK
-50mA
Package Thermal Impedance,
JA
50.04C/W (0 mfps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 2.5V 0.2V, T
A
= 0C
TO
70C
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83840AH
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2003
4
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
t
PD
V
DD
2
V
DD
2
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
V
DD
= 1.25V 0.1V
-1.25V 0.1V
P
ROPAGATION
D
ELAY
tsk(o)
V
DD
2
V
DD
2
nDPx
nDPy
D or H
H or D
tsk(o)
V
DD
2
V
DD
2
1.25V
1.25V
1.25V
V
OH
- 0.15V
V
OL
V
OH
0V
2.5V
t
PHZ
t
PZH
Output nDPx
(See Note)
Sn
(Low-level
enabling)
NOTE: The output is high except when disabled by the Sn control.
3-S
TATE
O
UTPUT
E
NABLE
/D
ISABLE
T
IMES
B
ANK
S
KEW
(
where X denotes outputs in the same bank
)
XDP0:XDP9
XDP0:XDP9
SCOPE
Qx
LVCMOS
V
DD
GND
This circuit is used for test purposes only,
not intended for application use.
83840AH
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2003
5
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS83840 is: 320
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
JA
by Velocity (Millimeter Feet per Second)
0
1
2
Two-Layer PCB, JEDEC Standard Test Boards
50.04C/W
43.18C/W
41.17C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
83840AH
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2003
6
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
P
ACKAGE
O
UTLINE
- H S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
R
EFERENCE
D
OCUMENT
: JEDEC P
UBLICATION
95
N
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C
S
B
0
0
.
7
1
E
C
S
B
0
0
.
5
e
C
S
B
0
5
.
0
83840AH
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2003
7
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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83840AH
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 22, 2003
8
Integrated
Circuit
Systems, Inc.
ICS83840
DDR SDRAM MUX
T
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