Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Clock Select Function Table
- Clock Input Function Table
- Absolute Maximum Ratings
- 3.3V DC Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V DC Characteristics
- 3.3V/2.5V AC Characteristics
- 2.5V DC Characteristics
- 2.5V AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 3.3V/2.5V Output Load AC Test Circuit Diagram
- 2.5V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Part-to-Part Skew Diagram
- Output Skew Diagram
- Propagation Delay Diagram
- 3.3V Output Rise/Fall Time Diagram
- 2.5V Output Rise/Fall Time Diagram
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Single Ended Signal Driving Differential Input Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
1
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS83940DI is a low skew, 1-to-18 LVPECL-
to-LVCMOS/LVTTL Fanout Buffer and a member
of the HiPerClockSTM family of High Performance
Clock Solutions from ICS. The ICS83940DI has
two selectable clock inputs. The PCLK, nPCLK
pair can accept LVPECL, CML, or SSTL input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed to
drive 50
series or parallel terminated transmission lines.
The ICS83940DI is characterized at 3.3V, 2.5V or mixed
3.3V core, 2.5V output operating supply modes. Guaranteed
output and part-to-part skew characteristics make the
ICS83940DI ideal for those clock distribution applications
demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
18 LVCMOS/LVTTL outputs
Selectable LVCMOS_CLK or LVPECL clock inputs
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 250MHz
Output skew: 150ps (maximum)
Part to part skew: 750ps (maximum)
3.3V, 2.5V or mixed 3.3V core, 2.5V output supply modes
-40C to 85C ambient operating temperature
Pin compatible with the MPC940L
HiPerClockSTM
,&6
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Pacakge
Top View
Q0:Q17
CLK_SEL
PCLK
nPCLK
LVCMOS_CLK
0
1
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q6
Q7
Q8
V
DD
Q9
Q10
Q11
GND
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
V
DD
V
DDO
V
DDO
Q12
Q13
Q14
GND
Q15
Q16
Q17
GND
Q5
Q4
Q3
V
DDO
Q2
Q1
Q0
ICS83940DI
18
83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
2
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
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83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
3
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
3.6V
Inputs, V
I
-0.3V to V
DD
+ 0.3V
Outputs, V
O
-0.3V to V
DDO
+ 0.3V
Input Current, I
IN
20mA
Storage Temperature, T
STG
-40C to 125C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
4
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
4A. DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V 5%, T
A
= -40
TO
85
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DD
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= -40
TO
85
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www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
5
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
4B. DC C
HARACTERISTICS
,
V
DD
= 3.3V 5%, V
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= 2.5V 5%, T
A
= -40
TO
85
T
ABLE
5B. AC C
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= 3.3V 5%, V
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83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
6
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
4C. DC C
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.
2
/
83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
7
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.05V5%
V
DDO
-1.25V5%
V
DD
1.25V5%
GND
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DD,
V
DDO
1.65V5%
-1.65V5%
GND
D
IFFERENTIAL
I
NPUT
L
EVEL
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
S
KEW
tsk(o)
V
DDO
2
V
DDO
2
Qy
Qx
SCOPE
Qx
LVCMOS
V
DD,
V
DDO
1.25V5%
-1.25V5%
GND
V
CMR
Cross Points
V
PP
GND
PCLK
nPCLK
V
DD
tsk(pp)
V
DDO
2
V
DDO
2
Qy
Qx
PART 2
PART 1
83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
8
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
P
ROPAGATION
D
ELAY
Q0:Q17
3.3V O
UTPUT
R
ISE
/F
ALL
T
IME
Clock Outputs
0.5V
2.4V
2.4V
0.5V
t
R
t
F
2.5V O
UTPUT
R
ISE
/F
ALL
T
IME
Clock Outputs
0.5V
1.8V
1.8V
0.5V
t
R
t
F
t
PD
V
DDO
2
V
DD
2
PCLK
nPCLK
LVCMOS_CLK
83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
9
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
10
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS83940DI is: 820
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
11
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
q
0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
Reference Document: JEDEC Publication 95, MS-026
83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
12
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
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83940DYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 12, 2002
13
Integrated
Circuit
Systems, Inc.
ICS83940DI
L
OW
S
KEW
, 1-
TO
-18
LVPECL-
TO
-LVCMOS / LVTTL F
ANOUT
B
UFFER
T
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