Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Output Enable & Clock Enable Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS 3.3V DC Characteristics
- LVCMOS 2.5V DC Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Additive Phase Jitter
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 2.5V Output Load AC Test Circulit Diagram
- Part-to-Part Skew Diagram
- Output Skew Diagram
- Propagation delay Diagram
- Ouput Duty Cycle/Pulse Width/Period Diagram
- 3.3V Output Rise/Fall Time Diagram
- 2.5V Output Rise/Fall Time Diagram
- Application Schematic Example
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
1
Integrated
Circuit
Systems, Inc.
ICS83947I-147
L
OW
S
KEW
, 1-
TO
-9
LVCMOS/LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS83947I-147 is a low skew, 1-to-9
LVCMOS/LVTTL Fanout Buffer and a member of
the HiPerClockSTM family of High Performance
Clock Solutions from ICS. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50
series or parallel terminated transmission lines. The effective
fanout can be increased from 9 to 18 by utilizing the ability of
the outputs to drive two series terminated lines.
Guaranteed output and part-to-part skew characteristics make
the ICS83947I-147 ideal for high performance, 3.3V or 2.5V
single ended applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
9 LVCMOS/LVTTL outputs
Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
Maximum output frequency: 250MHz
Output skew: 115ps (maximum)
Part-to-part skew: 500ps (maximum)
Additive phase jitter, RMS: 0.02ps (typical) @ 3.3V
Full 3.3V or 2.5V operating supply
-40C to 85C ambient operating temperature
Pin compatible with the MPC947
HiPerClockSTM
ICS
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
Q3
V
DDO
Q4
GND
Q5
V
DDO
GND
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
V
DD
GND
GND
Q6
V
DDO
Q7
GND
Q8
V
DDO
GND
GND
Q2
V
DDO
Q1
GND
Q0
V
DDO
GND
ICS83947I-147
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CLK0
CLK1
0
1
CLK_EN
CLK_SEL
D
Q
LE
OE
83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
2
Integrated
Circuit
Systems, Inc.
ICS83947I-147
L
OW
S
KEW
, 1-
TO
-9
LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. O
UTPUT
E
NABLE
AND
C
LOCK
E
NABLE
F
UNCTION
T
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83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
3
Integrated
Circuit
Systems, Inc.
ICS83947I-147
L
OW
S
KEW
, 1-
TO
-9
LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V0.3V
OR
2.5V5%, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V0.3V, T
A
= -40C
TO
85C
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A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V5%, T
A
= -40C
TO
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83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
4
Integrated
Circuit
Systems, Inc.
ICS83947I-147
L
OW
S
KEW
, 1-
TO
-9
LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V0.3V, T
A
= -40C
TO
85C
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83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
5
Integrated
Circuit
Systems, Inc.
ICS83947I-147
L
OW
S
KEW
, 1-
TO
-9
LVCMOS/LVTTL F
ANOUT
B
UFFER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a
dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
Additive Phase Jitter, RMS
@
156.25MHz (12KHz to 20MHz)
= 0.01ps typical @ 2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dBc/H
Z
Additive Phase Jitter, RMS
@
156.25MHz (12KHz to 20MHz)
= 0.02ps typical @ 3.3V
83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
6
Integrated
Circuit
Systems, Inc.
ICS83947I-147
L
OW
S
KEW
, 1-
TO
-9
LVCMOS/LVTTL F
ANOUT
B
UFFER
t
PD
V
DD
2
V
DDO
2
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V 0.15V
-1.65V 0.15V
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Clock
Outputs
0.8V
2V
2V
0.8V
t
R
t
F
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
O
UTPUT
S
KEW
tsk(pp)
V
DDO
2
V
DDO
2
Qx
Qy
PART 1
PART 2
CLK0,CLK1
Q0:Q8
Q0:Q8
3.3V O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
t
PW
t
PERIOD
V
DDO
2
V
DDO
2
V
DDO
2
t
PW
t
PERIOD
odc =
V
DD
,
V
DDO
V
DD
,
V
DDO
2.5V O
UTPUT
R
ISE
/F
ALL
T
IME
GND
GND
83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
7
Integrated
Circuit
Systems, Inc.
ICS83947I-147
L
OW
S
KEW
, 1-
TO
-9
LVCMOS/LVTTL F
ANOUT
B
UFFER
A
PPLICATION
S
CHEMATIC
E
XAMPLE
Figure 1 shows an example of ICS83947I-147 application sche-
matic. In this example, the device is operated at V
CC
=3.3V. The
decoupling capacitors should be located as close as possible
to the power pin. The input is driven by a 3.3V LVCMOS driver.
C4
0.1u
VCC
Zo = 50 Ohm
R3
43
R2
43
R1
43
C2
0.1u
(U1-22)
C3
0.1u
C1
0.1u
C3
0.1u
(U1-10)
VDDO
(U1-18)
C5
0.1u
VDDO
(U1-14)
Zo = 50
U1
ICS83947I-147
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
GND
CLK_SEL
CLK0
CLK1
CLK_EN
OE
VDD
GND
GN
D
V
DDO
Q8
GN
D
Q7
V
DDO
Q6
GN
D
GND
VDDO
Q5
GND
Q4
VDDO
Q3
GND
GN
D
V
DDO
Q0
GN
D
Q1
V
DDO
Q2
GN
D
VCC
VDD=3.3V
LVCMOS
Zo = 50
Zo = 50 Ohm
(U1-27)
VDD
VDDO=3.3V
LVCMOS
C2
0.1u
(U1-31)
R3
43
For the LVCMOS output drivers, only one termination example
is shown in this schematic. Additional termination approaches
are shown in the LVCMOS Termination Application Note (refer
to ICS website).
F
IGURE
1. ICS83947I-147 S
CHEMATIC
L
AYOUT
83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
8
Integrated
Circuit
Systems, Inc.
ICS83947I-147
L
OW
S
KEW
, 1-
TO
-9
LVCMOS/LVTTL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS83947I-147 is: 1040
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
9
Integrated
Circuit
Systems, Inc.
ICS83947I-147
L
OW
S
KEW
, 1-
TO
-9
LVCMOS/LVTTL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
Reference Document: JEDEC Publication 95, MS-026
83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
10
Integrated
Circuit
Systems, Inc.
ICS83947I-147
L
OW
S
KEW
, 1-
TO
-9
LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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