83948AYI-01
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 23, 2002
1
Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS83948I-01 is a low skew, 1-to-12 Differ-
ential-to-LVCMOS Fanout Buffer and a member
of the HiPerClockSTM family of High Performance
Clock Solutions from ICS. The ICS83948I-01 has
two selectable clock inputs. The CLK, nCLK pair
can accept most standard differential input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS outputs are designed to drive
50
series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
The ICS83948I-01 is characterized at 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics make
the ICS83948I-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
12 LVCMOS outputs
Selectable LVCMOS clock or differential CLK, nCLK inputs
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 150MHz
Output skew: 350ps (maximum)
Part to part skew: 1.5ns (maximum)
3.3V core, 3.3V output
-40C to 85C ambient operating temperature
Pin compatible with the MPC948/948L
HiPerClockSTM
,&6
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
GND
GND
Q8
V
DDO
Q9
GND
Q10
V
DDO
Q11
Q3
V
DDO
Q2
GND
Q1
V
DDO
Q0
GND
ICS83948I-01
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
LVCMOS_CLK
CLK
nCLK
1
0
CLK_EN
CLK_SEL
D
Q
OE
83948AYI-01
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 23, 2002
2
Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
r
e
b
m
u
N
e
m
a
N
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
1
L
E
S
_
K
L
C
t
u
p
n
I
p
u
ll
u
P
t
u
p
n
i
k
c
o
l
c
S
O
M
C
V
L
s
t
c
e
l
e
S
.
t
u
p
n
i
t
c
e
l
e
s
k
c
o
l
C
.
W
O
L
n
e
h
w
s
t
u
p
n
i
K
L
C
n
,
K
L
C
s
t
c
e
l
e
S
.
H
G
I
H
n
e
h
w
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
2
K
L
C
_
S
O
M
C
V
L
t
u
p
n
I
p
u
ll
u
P
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
t
u
p
n
i
k
c
o
l
C
3
K
L
C
t
u
p
n
I
p
u
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
g
n
i
t
r
e
v
n
i
-
n
o
N
4
K
L
C
n
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
l
a
i
t
n
e
r
e
f
f
i
d
g
n
i
t
r
e
v
n
I
5
N
E
_
K
L
C
t
u
p
n
I
p
u
ll
u
P
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
e
l
b
a
n
e
k
c
o
l
C
6
E
O
t
u
p
n
I
p
u
ll
u
P
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
e
l
b
a
n
e
t
u
p
t
u
O
7
V
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
e
r
o
C
,
6
1
,
2
1
,
8
2
3
,
8
2
,
4
2
,
0
2
D
N
G
r
e
w
o
P
.
d
n
u
o
r
g
y
l
p
p
u
s
r
e
w
o
P
,
5
1
,
3
1
,
1
1
,
9
3
2
,
1
2
,
9
1
,
7
1
1
3
,
9
2
,
7
2
,
5
2
,
8
Q
,
9
Q
,
0
1
Q
,
1
1
Q
,
4
Q
,
5
Q
,
6
Q
,
7
Q
0
Q
,
1
Q
,
2
Q
,
3
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
s
t
u
p
t
u
o
k
c
o
l
C
0
3
,
6
2
,
2
2
,
8
1
,
4
1
,
0
1
V
O
D
D
r
e
w
o
P
.
s
n
i
p
y
l
p
p
u
s
t
u
p
t
u
O
:
E
T
O
N
p
u
ll
u
P
d
n
a
n
w
o
d
ll
u
P
.
s
e
u
l
a
v
l
a
c
i
p
y
t
r
o
f
,
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
n
i
P
,
2
e
l
b
a
T
e
e
S
.
s
r
o
t
s
i
s
e
r
t
u
p
n
i
l
a
n
r
e
t
n
i
o
t
r
e
f
e
r
T
ABLE
2. P
IN
C
HARACTERISTICS
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
C
N
I
e
c
n
a
t
i
c
a
p
a
C
t
u
p
n
I
4
F
p
C
D
P
e
c
n
a
t
i
c
a
p
a
C
n
o
i
t
a
p
i
s
s
i
D
r
e
w
o
P
)
t
u
p
t
u
o
r
e
p
(
5
2
F
p
R
P
U
L
L
U
P
r
o
t
s
i
s
e
R
p
u
ll
u
P
t
u
p
n
I
1
5
K
R
N
W
O
D
L
L
U
P
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
t
u
p
n
I
1
5
K
R
T
U
O
e
c
n
a
d
e
p
m
I
t
u
p
t
u
O
7
T
ABLE
3A. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
t
u
p
n
I
l
o
r
t
n
o
C
k
c
o
l
C
L
E
S
_
K
L
C
K
L
C
n
,
K
L
C
K
L
C
_
S
O
M
C
V
L
0
d
e
t
c
e
l
e
S
d
e
t
c
e
l
e
s
-
e
D
1
d
e
t
c
e
l
e
s
-
e
D
d
e
t
c
e
l
e
S
s
t
u
p
n
I
s
t
u
p
t
u
O
e
d
o
M
t
u
p
t
u
O
o
t
t
u
p
n
I
y
t
i
r
a
l
o
P
L
E
S
_
K
L
C
K
L
C
_
S
O
M
C
V
L
K
L
C
K
L
C
n
2
1
Q
:
0
Q
0
--
0
1
W
O
L
d
e
d
n
E
e
l
g
n
i
S
o
t
l
a
i
t
n
e
r
e
f
f
i
D
g
n
i
t
r
e
v
n
I
n
o
N
0
--
1
0
H
G
I
H
d
e
d
n
E
e
l
g
n
i
S
o
t
l
a
i
t
n
e
r
e
f
f
i
D
g
n
i
t
r
e
v
n
I
n
o
N
0
--
0
1
E
T
O
N
;
d
e
s
a
i
B
W
O
L
d
e
d
n
E
e
l
g
n
i
S
o
t
d
e
d
n
E
e
l
g
n
i
S
g
n
i
t
r
e
v
n
I
n
o
N
0
--
1
1
E
T
O
N
;
d
e
s
a
i
B
H
G
I
H
d
e
d
n
E
e
l
g
n
i
S
o
t
d
e
d
n
E
e
l
g
n
i
S
g
n
i
t
r
e
v
n
I
n
o
N
0
--
1
E
T
O
N
;
d
e
s
a
i
B
0
H
G
I
H
d
e
d
n
E
e
l
g
n
i
S
o
t
d
e
d
n
E
e
l
g
n
i
S
g
n
i
t
r
e
v
n
I
0
--
1
E
T
O
N
;
d
e
s
a
i
B
1
W
O
L
d
e
d
n
E
e
l
g
n
i
S
o
t
d
e
d
n
E
e
l
g
n
i
S
g
n
i
t
r
e
v
n
I
1
0
--
--
W
O
L
d
e
d
n
E
e
l
g
n
i
S
o
t
d
e
d
n
E
e
l
g
n
i
S
g
n
i
t
r
e
v
n
I
n
o
N
1
1
--
--
H
G
I
H
d
e
d
n
E
e
l
g
n
i
S
o
t
d
e
d
n
E
e
l
g
n
i
S
g
n
i
t
r
e
v
n
I
n
o
N
.
"
s
l
e
v
e
L
d
e
d
n
E
e
l
g
n
i
S
t
p
e
c
c
A
o
t
t
u
p
n
I
l
a
i
t
n
e
r
e
f
f
i
D
e
h
t
g
n
i
r
i
W
"
,
n
o
i
t
c
e
s
n
o
i
t
a
m
r
o
f
n
I
n
o
i
t
a
c
il
p
p
A
e
h
t
o
t
r
e
f
e
r
e
s
a
e
l
P
:
1
E
T
O
N
83948AYI-01
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 23, 2002
3
Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, Tstg
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V0.3V, T
A
= -40
TO
85
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
n
I
0
.
3
3
.
3
6
.
3
V
V
O
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
0
.
3
3
.
3
6
.
3
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
t
n
e
c
s
e
i
u
Q
5
5
A
m
T
ABLE
4B. DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V0.3V, T
A
= -40
TO
85
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
L
T
T
V
L
/
S
O
M
C
V
L
2
6
.
3
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
L
T
T
V
L
/
S
O
M
C
V
L
8
.
0
V
V
P
P
e
g
a
t
l
o
V
t
u
p
n
I
k
a
e
P
-
o
t
-
k
a
e
P
K
L
C
n
,
K
L
C
5
1
.
0
3
.
1
V
V
R
M
C
;
e
g
a
t
l
o
V
e
d
o
M
n
o
m
m
o
C
t
u
p
n
I
2
,
1
E
T
O
N
K
L
C
n
,
K
L
C
5
.
0
+
D
N
G
V
D
D
5
8
.
0
-
V
I
N
I
t
n
e
r
r
u
C
t
u
p
n
I
0
0
1
A
V
H
O
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
I
H
O
A
m
0
2
-
=
5
.
2
V
V
L
O
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
I
L
O
A
m
0
2
=
4
.
0
V
s
i
K
L
C
n
,
K
L
C
r
o
f
e
g
a
t
l
o
v
t
u
p
n
i
m
u
m
i
x
a
m
e
h
t
,
s
n
o
i
t
a
c
il
p
p
a
d
e
d
n
e
e
l
g
n
i
s
r
o
F
:
1
E
T
O
N
V
D
D
.
V
3
.
0
+
s
a
d
e
n
i
f
e
d
s
i
e
g
a
t
l
o
v
e
d
o
m
n
o
m
m
o
C
:
2
E
T
O
N
V
H
I
.
83948AYI-01
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 23, 2002
4
Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V0.3V, T
A
= -40
TO
85
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
X
A
M
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
m
u
m
i
x
a
M
0
5
1
z
H
M
t
D
P
y
a
l
e
D
n
o
i
t
a
g
a
p
o
r
P
;
K
L
C
n
,
K
L
C
A
1
E
T
O
N
5
.
2
5
.
6
s
n
;
K
L
C
_
S
O
M
C
V
L
B
1
E
T
O
N
3
5
.
5
s
n
t
)
o
(
k
s
6
,
2
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
n
o
d
e
r
u
s
a
e
M
V
@
e
g
d
e
g
n
i
s
i
r
O
D
D
2
/
0
5
3
s
p
t
)
p
p
(
k
s
;
w
e
k
S
t
r
a
P
-
o
t
-
t
r
a
P
6
,
3
E
T
O
N
K
L
C
n
,
K
L
C
n
o
d
e
r
u
s
a
e
M
V
@
e
g
d
e
g
n
i
s
i
r
O
D
D
2
/
5
.
1
s
n
K
L
C
_
S
O
M
C
V
L
2
s
n
t
R
e
m
i
T
e
s
i
R
t
u
p
t
u
O
V
2
o
t
V
8
.
0
2
.
0
0
.
1
s
n
t
F
e
m
i
T
ll
a
F
t
u
p
t
u
O
V
2
o
t
V
8
.
0
2
.
0
0
.
1
s
n
t
W
P
h
t
d
i
W
e
s
l
u
P
t
u
p
t
u
O
0
0
8
-
2
/
d
o
i
r
e
P
t
0
0
8
+
2
/
d
o
i
r
e
P
t
s
p
t
L
Z
P
t
,
H
Z
P
4
E
T
O
N
;
e
m
i
T
e
l
b
a
s
i
D
t
u
p
t
u
O
1
1
s
n
t
Z
L
P
t
,
Z
H
P
4
E
T
O
N
;
e
m
i
T
e
l
b
a
n
E
t
u
p
t
u
O
1
1
s
n
t
S
e
l
b
a
n
E
k
c
o
l
C
;
e
m
i
T
p
u
t
e
S
5
E
T
O
N
o
t
N
E
_
K
L
C
K
L
C
1
s
n
o
t
N
E
_
K
L
C
K
L
C
_
S
O
M
C
V
L
0
s
n
t
H
e
l
b
a
n
E
k
c
o
l
C
;
e
m
i
T
d
l
o
H
5
E
T
O
N
o
t
K
L
C
N
E
_
K
L
C
0
s
n
K
L
C
_
S
O
M
C
V
L
N
E
_
K
L
C
o
t
1
s
n
o
t
t
n
i
o
p
g
n
i
s
s
o
r
c
t
u
p
n
i
l
a
i
t
n
e
r
e
f
f
i
d
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
A
1
E
T
O
N
V
O
D
D
.
t
u
p
t
u
o
e
h
t
f
o
2
/
e
h
t
m
o
r
f
d
e
r
u
s
a
e
M
:
B
1
E
T
O
N
V
D
D
o
t
t
u
p
n
i
e
h
t
f
o
2
/
V
O
D
D
2
/
.
t
u
p
t
u
o
e
h
t
f
o
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
2
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
O
D
D
.
2
/
h
t
i
w
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
g
n
i
t
a
r
e
p
o
s
e
c
i
v
e
d
t
n
e
r
e
f
f
i
d
n
o
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
3
E
T
O
N
V
t
a
d
e
r
u
s
a
e
m
e
r
a
s
t
u
p
t
u
o
e
h
t
,
e
c
i
v
e
d
h
c
a
e
n
o
s
t
u
p
n
i
f
o
e
p
y
t
e
m
a
s
e
h
t
g
n
i
s
U
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
O
D
D
.
2
/
.
n
o
i
t
c
u
d
o
r
p
n
i
d
e
t
s
e
t
t
o
N
.
n
o
i
t
a
z
i
r
e
t
c
a
r
a
h
c
y
b
d
e
e
t
n
a
r
a
u
g
e
r
a
s
r
e
t
e
m
a
r
a
p
e
s
e
h
T
:
4
E
T
O
N
.
k
c
o
l
c
t
u
p
n
i
e
h
t
f
o
e
g
d
e
g
n
il
l
a
f
e
h
t
o
t
e
v
i
t
a
l
e
r
e
r
a
s
e
m
i
t
d
l
o
H
d
n
a
p
u
t
e
S
:
5
E
T
O
N
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
6
E
T
O
N
83948AYI-01
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 23, 2002
5
Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
-1.65V0.15V
GND
V
DD,
V
DDO
1.65V0.15V
D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
nCLK
CLK
GND
V
DD
83948AYI-01
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 23, 2002
6
Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
O
UTPUT
R
ISE
AND
F
ALL
T
IME
Clock Outputs
0.8V
2V
2V
0.8V
t
R
t
F
O
UTPUT
S
KEW
Qx
Qy
tsk(o)
V
DDO
2
V
DDO
2
P
ART
-
TO
-P
ART
S
KEW
Qx
Qy
PART 1
PART 2
tsk(pp)
V
DDO
2
V
DDO
2
83948AYI-01
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 23, 2002
7
Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
t
PW
& t
P
ERIOD
Q0:Q11
t
PW
t
PERIOD
V
DDO
2
V
DDO
2
V
DDO
2
t
PW
t
PERIOD
odc =
P
ROPAGATION
D
ELAY
nCLK
CLK
Q0:Q11
t
PD
V
DDO
2
V
DD
2
LVCMOS_CLK
83948AYI-01
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 23, 2002
8
Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
F
IGURE
2 - S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
83948AYI-01
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 23, 2002
9
Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS83948I-01 is: 1040
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
83948AYI-01
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 23, 2002
10
Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
q
0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
R
EFERENCE
D
OCUMENT
: JEDEC P
UBLICATION
95, MS-026
83948AYI-01
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 23, 2002
11
Integrated
Circuit
Systems, Inc.
ICS83948I-01
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
a
M
e
g
a
k
c
a
P
t
n
u
o
C
e
r
u
t
a
r
e
p
m
e
T
1
0
-
I
Y
A
8
4
9
3
8
S
C
I
1
0
I
Y
A
8
4
9
3
8
S
C
I
P
F
Q
L
d
a
e
L
2
3
y
a
r
t
r
e
p
0
5
2
C
5
8
o
t
C
0
4
-
T
1
0
-
I
Y
A
8
4
9
3
8
S
C
I
1
0
I
Y
A
8
4
9
3
8
S
C
I
l
e
e
R
d
n
a
e
p
a
T
n
o
P
F
Q
L
d
a
e
L
2
3
0
0
0
1
C
5
8
o
t
C
0
4
-
PDF 
ZIP