83948AYI-147
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2005
1
Integrated
Circuit
Systems, Inc.
ICS83948I-147
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS83948I-147 is a low skew, 1-to-12
Differential-to-LVCMOS/LVTTL Fanout Buffer and
a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
ICS83948I-147 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential
input levels. The LVCMOS_CLK can accept LVCMOS or
LVTTL input levels. The low impedance LVCMOS/LVTTL out-
puts are designed to drive 50
series or parallel terminated
transmission lines. The effective fanout can be increased
from 12 to 24 by utilizing the ability of the outputs to drive two
series terminated lines.
The ICS83948I-147 is characterized at full 3.3V or full 2.5V
operating supply modes. Guaranteed output and part-to-part
skew characteristics make the ICS83948I-147 ideal for those
clock distribution applications demanding well defined per-
formance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Twelve LVCMOS/LVTTL outputs
Selectable LVCMOS/LVTTL clock
or differential CLK, nCLK inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
Output frequency: 350MHz (maximum)
Output skew (at 3.3V 5%): 100ps (maximum)
Part-to-part skew (at 3.3V 5%): 1ns (maximum)
Full 3.3V or full 2.5V operating supply
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
HiPerClockSTM
ICS
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
GND
GND
Q8
V
DDO
Q9
GND
Q10
V
DDO
Q11
Q3
V
DDO
Q2
GND
Q1
V
DDO
Q0
GND
ICS83948I-147
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
LVCMOS_CLK
CLK
nCLK
1
0
CLK_EN
CLK_SEL
D
Q
LE
OE
83948AYI-147
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2005
2
Integrated
Circuit
Systems, Inc.
ICS83948I-147
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3A. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
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ABLE
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83948AYI-147
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2005
3
Integrated
Circuit
Systems, Inc.
ICS83948I-147
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40
TO
85
T
ABLE
4C. DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40
TO
85
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. P
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S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V5%, T
A
= -40
TO
85
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A
m
83948AYI-147
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2005
4
Integrated
Circuit
Systems, Inc.
ICS83948I-147
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
5A. AC C
HARACTERISTICS
,
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DD
= V
DDO
= 3.3V5%, T
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= -40
TO
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.
83948AYI-147
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2005
5
Integrated
Circuit
Systems, Inc.
ICS83948I-147
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
5B. AC C
HARACTERISTICS
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83948AYI-147
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2005
6
Integrated
Circuit
Systems, Inc.
ICS83948I-147
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V 5%
-1.65V 5%
SCOPE
Qx
LVCMOS
V
DD
,
V
DDO
-1.25V5%
D
IFFERENTIAL
I
NPUT
L
EVEL
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
V
DD
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
odc & t
P
ERIOD
Clock
Outputs
0.8V
2V
2V
0.8V
t
R
t
F
t
sk(o)
V
DDO
2
V
DDO
2
Qx
Qy
O
UTPUT
S
KEW
t
sk(pp)
V
DDO
2
V
DDO
2
Qx
Qy
PART 1
PART 2
nCLK
CLK
Q0:Q11
t
PD
V
DDO
2
V
DD
2
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
Q0:Q11
LVCMOS_CLK
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
0.6V
1.8V
1.8V
0.6V
t
R
t
F
V
DD
=
V
DDO
= 3.3V
V
DD
=
V
DDO
= 2.5V
1.25V5%
GND
GND
V
DD
,
V
DDO
83948AYI-147
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2005
7
Integrated
Circuit
Systems, Inc.
ICS83948I-147
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
I
NPUTS
:
CLK I
NPUT
:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the CLK input to
ground.
CLK/nCLK I
NPUT
:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
resistor can be tied from
CLK to ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
83948AYI-147
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2005
8
Integrated
Circuit
Systems, Inc.
ICS83948I-147
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS83948I-147 is: 1040
Pin compatible with the MPC9448
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
83948AYI-147
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2005
9
Integrated
Circuit
Systems, Inc.
ICS83948I-147
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
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M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
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0
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-
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.
0
D
C
I
S
A
B
0
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9
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C
I
S
A
B
0
0
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7
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.
f
e
R
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5
E
C
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A
B
0
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C
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S
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7
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E
.
f
e
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e
C
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0
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7
c
c
c
-
-
-
-
0
1
.
0
R
EFERENCE
D
OCUMENT
: JEDEC P
UBLICATION
95, MS-026
83948AYI-147
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2005
10
Integrated
Circuit
Systems, Inc.
ICS83948I-147
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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O
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83948AYI-147
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2005
11
Integrated
Circuit
Systems, Inc.
ICS83948I-147
L
OW
S
KEW
, 1-
TO
-12
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
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