Document Outline
- General Description
- Features
- Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 2.5V DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise at 106.25MHz
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Layout Guideline
- Schematic Example
- PC Board Layout Example
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
1
Integrated
Circuit
Systems, Inc.
ICS840001I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS840001I is a Fibre Channel Clock
Generator and a member of the HiPerClocks
TM
family of high performance devices from ICS. The
ICS840001I uses a 26.5625MHz crystal to
synthesize either 106.25MHz or 212.5MHz, using
the FREQ_SEL pin. The ICS840001I has excellent phase jitter
performance, over the 637kHz 5MHz integration range. The
ICS840001I is packaged in a small 8-pin TSSOP, making it
ideal for use in systems with limited board space.
F
EATURES
1 LVCMOS/LVTTL output, 7 typical output impedence
Crystal oscillator interface designed for 26.5625MHz,
18pF parallel resonant crystal
Selectable 106.25MHz or 212.5MHz output frequency
VCO range: 560MHz to 680MHz
RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 5MHz): 0.70ps (typical)
3.3V or 2.5V operating supply
-40C to 85C ambient operating temperature
HiPerClockSTM
ICS
ICS840001I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
V
DDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
V
DD
Q
GND
FREQ_SEL
8
7
6
5
t
u
p
n
I
s
e
i
c
n
e
u
q
e
r
F
t
u
p
t
u
O
L
E
S
_
Q
E
R
F
0
)
t
l
u
a
f
e
D
(
z
H
M
5
2
.
6
0
1
1
z
H
M
5
.
2
1
2
z
H
M
5
2
6
5
.
6
2
:
l
a
t
s
y
r
C
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
UNCTION
T
ABLE
OSC
Phase
Detector
VCO
637.5MHz w/
26.5625MHz Ref.
M = 24 (fixed)
1
0
6
3
XTAL_IN
XTAL_OUT
OE
Q
FREQ_SEL
(Pullup)
(Pulldown)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
2
Integrated
Circuit
Systems, Inc.
ICS840001I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
1. P
IN
D
ESCRIPTIONS
r
e
b
m
u
N
e
m
a
N
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
1
V
A
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
g
o
l
a
n
A
2
E
O
t
u
p
n
I
p
u
ll
u
P
.
d
e
l
b
a
n
e
s
i
t
u
p
t
u
o
Q
,
H
G
I
H
n
e
h
W
.
n
i
p
e
l
b
a
n
e
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
e
t
a
t
s
Z
i
H
o
t
Q
s
e
c
r
o
f
,
W
O
L
n
e
h
W
4
,
3
,
T
U
O
_
L
A
T
X
N
I
_
L
A
T
X
t
u
p
n
I
.
t
u
p
n
i
e
h
t
s
i
N
I
_
L
A
T
X
.
e
c
a
f
r
e
t
n
i
r
o
t
a
ll
i
c
s
o
l
a
t
s
y
r
C
.
t
u
p
t
u
o
e
h
t
s
i
T
U
O
_
L
A
T
X
5
L
E
S
_
Q
E
R
F
t
u
p
n
I
n
w
o
d
ll
u
P
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
n
i
p
t
c
e
l
e
s
y
c
n
e
u
q
e
r
F
6
D
N
G
r
e
w
o
P
.
d
n
u
o
r
g
y
l
p
p
u
s
r
e
w
o
P
7
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
t
u
p
t
u
o
k
c
o
l
c
d
e
d
n
e
-
e
l
g
n
i
S
7
.
e
c
n
a
d
e
p
m
i
t
u
p
t
u
o
l
a
c
i
p
y
t
8
V
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
e
r
o
C
:
E
T
O
N
p
u
ll
u
P
d
n
a
n
w
o
d
ll
u
P
.
s
e
u
l
a
v
l
a
c
i
p
y
t
r
o
f
,
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
n
i
P
,
2
e
l
b
a
T
e
e
S
.
s
r
o
t
s
i
s
e
r
t
u
p
n
i
l
a
n
r
e
t
n
i
o
t
r
e
f
e
r
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
C
N
I
e
c
n
a
t
i
c
a
p
a
C
t
u
p
n
I
4
F
p
C
D
P
e
c
n
a
t
i
c
a
p
a
C
n
o
i
t
a
p
i
s
s
i
D
r
e
w
o
P
V
D
D
V
,
A
D
D
V
5
6
4
.
3
=
D
B
T
F
p
V
D
D
V
,
A
D
D
V
5
2
6
.
2
=
D
B
T
F
p
R
P
U
L
L
U
P
r
o
t
s
i
s
e
R
p
u
ll
u
P
t
u
p
n
I
1
5
k
R
N
W
O
D
L
L
U
P
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
t
u
p
n
I
1
5
k
R
T
U
O
e
c
n
a
d
e
p
m
I
t
u
p
t
u
O
5
7
2
1
T
ABLE
3. C
ONTROL
F
UNCTION
T
ABLE
s
t
u
p
n
I
l
o
r
t
n
o
C
t
u
p
t
u
O
E
O
Q
0
Z
-
i
H
1
e
v
i
t
c
A
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
3
Integrated
Circuit
Systems, Inc.
ICS840001I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
5
7
A
m
I
A
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
8
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%
OR
2.5V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
V
D
D
V
3
.
3
=
2
V
D
D
3
.
0
+
V
V
D
D
V
5
.
2
=
7
.
1
V
D
D
3
.
0
+
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
V
D
D
V
3
.
3
=
3
.
0
-
8
.
0
V
V
D
D
V
5
.
2
=
3
.
0
-
7
.
0
V
I
H
I
t
n
e
r
r
u
C
h
g
i
H
t
u
p
n
I
L
E
S
_
Q
E
R
F
V
D
D
V
=
N
I
V
5
2
6
.
2
r
o
V
5
6
4
.
3
=
0
5
1
A
E
O
V
D
D
V
=
N
I
V
5
2
6
.
2
r
o
V
5
6
4
.
3
=
5
A
I
L
I
t
n
e
r
r
u
C
w
o
L
t
u
p
n
I
L
E
S
_
Q
E
R
F
V
D
D
V
,
V
5
2
6
.
2
r
o
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
E
O
V
D
D
V
,
V
5
2
6
.
2
r
o
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
V
H
O
1
E
T
O
N
;
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
V
D
D
V
5
6
4
.
3
=
6
.
2
V
V
D
D
V
5
2
6
.
2
=
8
.
1
V
V
L
O
1
E
T
O
N
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
V
D
D
V
5
2
6
.
2
r
o
V
5
6
4
.
3
=
5
.
0
V
0
5
h
t
i
w
d
e
t
a
n
i
m
r
e
t
s
t
u
p
t
u
O
:
1
E
T
O
N
V
o
t
D
D
,
n
o
i
t
c
e
S
n
o
i
t
a
m
r
o
f
n
I
t
n
e
m
e
r
u
s
a
e
M
r
e
t
e
m
a
r
a
P
e
e
S
.
2
/
.
s
m
a
r
g
a
i
d
"
t
i
u
c
r
i
C
t
s
e
T
d
a
o
L
t
u
p
t
u
O
"
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
7
3
.
2
5
.
2
5
2
6
.
2
V
V
A
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
7
3
.
2
5
.
2
5
2
6
.
2
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
3
7
A
m
I
A
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
8
A
m
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
4
Integrated
Circuit
Systems, Inc.
ICS840001I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
6A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
T
U
O
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
1
=
L
E
S
_
Q
E
R
F
6
6
.
6
8
1
5
.
2
1
2
6
6
.
6
2
2
z
H
M
0
=
L
E
S
_
Q
E
R
F
3
3
.
3
9
5
2
.
6
0
1
3
3
.
3
1
1
z
H
M
t
)
(
t
ij
;
)
m
o
d
n
a
R
(
r
e
t
t
i
J
e
s
a
h
P
S
M
R
1
E
T
O
N
,
z
H
M
5
2
.
6
0
1
=
T
U
O
f
)
z
H
M
5
o
t
z
H
k
7
3
6
(
0
7
.
0
s
p
,
z
H
M
5
.
2
1
2
=
T
U
O
f
)
z
H
M
0
2
o
t
z
H
M
5
5
.
2
(
0
5
.
0
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
0
4
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
0
5
%
.
z
H
M
5
2
.
6
0
1
d
n
a
z
H
M
5
.
2
1
2
@
d
e
z
i
r
e
t
c
a
r
a
h
c
e
r
a
s
r
e
t
e
m
a
r
a
p
ll
A
.
n
o
i
t
c
e
s
s
i
h
t
g
n
i
w
o
ll
o
f
s
t
o
l
P
e
s
i
o
N
e
s
a
h
P
e
h
t
o
t
r
e
f
e
r
e
s
a
e
l
P
:
1
E
T
O
N
T
ABLE
6B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
T
U
O
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
1
=
L
E
S
_
Q
E
R
F
6
6
.
6
8
1
5
.
2
1
2
6
6
.
6
2
2
z
H
M
0
=
L
E
S
_
Q
E
R
F
3
3
.
3
9
5
2
.
6
0
1
3
3
.
3
1
1
z
H
M
t
)
(
t
ij
;
)
m
o
d
n
a
R
(
r
e
t
t
i
J
e
s
a
h
P
S
M
R
1
E
T
O
N
,
z
H
M
5
2
.
6
0
1
=
T
U
O
f
)
z
H
M
5
o
t
z
H
k
7
3
6
(
0
7
.
0
s
p
,
z
H
M
5
.
2
1
2
=
T
U
O
f
)
z
H
M
0
2
o
t
z
H
M
5
5
.
2
(
0
5
.
0
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
5
4
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
0
5
%
.
z
H
M
5
2
.
6
0
1
d
n
a
z
H
M
5
.
2
1
2
@
d
e
z
i
r
e
t
c
a
r
a
h
c
e
r
a
s
r
e
t
e
m
a
r
a
p
ll
A
.
n
o
i
t
c
e
s
s
i
h
t
g
n
i
w
o
ll
o
f
s
t
o
l
P
e
s
i
o
N
e
s
a
h
P
e
h
t
o
t
r
e
f
e
r
e
s
a
e
l
P
:
1
E
T
O
N
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
n
o
i
t
a
ll
i
c
s
O
f
o
e
d
o
M
l
a
t
n
e
m
a
d
n
u
F
y
c
n
e
u
q
e
r
F
5
2
6
5
.
6
2
z
H
M
)
R
S
E
(
e
c
n
a
t
s
i
s
e
R
s
e
i
r
e
S
t
n
e
l
a
v
i
u
q
E
0
5
e
c
n
a
t
i
c
a
p
a
C
t
n
u
h
S
7
F
p
l
e
v
e
L
e
v
i
r
D
1
W
m
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
5
Integrated
Circuit
Systems, Inc.
ICS840001I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
106.25MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
106.25MHz
RMS Phase Jitter (Random)
637kHz to 5MHz = 0.70ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
Fibre Channel Filter
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
6
Integrated
Circuit
Systems, Inc.
ICS840001I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V 5%
-1.65V 5%
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
x 100%
t
PW
Q
GND
V
DD
,
V
DDA
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
RMS P
HASE
J
ITTER
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
V
DD
,
V
DDA
GND
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
7
Integrated
Circuit
Systems, Inc.
ICS840001I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
A
PPLICATION
I
NFORMATION
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS840001I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 26.5625MHz, 18pF par-
allel resonant crystal and were chosen to minimize the ppm er-
ror. The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS840001I provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V
DD
and V
DDA
should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required.
Figure 1
illustrates how a 10
resistor along with a 10F and a .01F
bypass capacitor should be connected to each V
DDA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V or 2.5V
.01
F
V
DD
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
8
Integrated
Circuit
Systems, Inc.
ICS840001I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
L
AYOUT
G
UIDELINE
Figure 3A shows a schematic example of the ICS840001I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18
pF parallel resonant 26.5625MHz crystal is used. The C1=27pF
and C2=33pF are recommended for frequency accuracy. For
F
IGURE
3A. ICS840001I S
CHEMATIC
E
XAMPLE
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy. The output frequency can be
set at either 106.25MHz or 212.5MHz. Leaving the R1 un-in-
stalled (or install 1k
pull-down) will set the output frequency at
106.25MHz. Installing the R1 pull up will set the output frequency
at 212.5MHz.
PC B
OARD
L
AYOUT
E
XAMPLE
Figure 3B shows an example of P.C. board layout. The crystal
X1 footprint in this example allows either surface mount (HC49S)
or through hole (HC49) package. C3 is 0805. C1 and C2 are
0402. Other resistors and capacitors are 0603. This layout as-
sumes that the board has clean analog power and ground planes.
F
IGURE
3B. ICS840001I PC B
OARD
L
AYOUT
E
XAMPLE
LVCMOS
VDD=3.3V
U2
840001I
1
2
3
4
8
7
6
5
VDDA
OE
XTAL_OUT
XTAL_IN
VDD
Q
GND
FREQ_SEL
C5
0.1u
R1
1K
R2
10
C3
10uF
VDD
VDD
C2
33pF
FRE_SEL
VDD
C4
0.1u
Zo = 50 Ohm
OE
Q
R3
43
VDDA
C1
27pF
X1
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
9
Integrated
Circuit
Systems, Inc.
ICS840001I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS840001I is: 1521
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters Per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
10
Integrated
Circuit
Systems, Inc.
ICS840001I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
8
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
9
.
2
0
1
.
3
E
C
I
S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
840001AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 20, 2005
11
Integrated
Circuit
Systems, Inc.
ICS840001I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
a
M
e
g
a
k
c
a
P
g
n
i
g
a
k
c
a
P
g
n
i
p
p
i
h
S
e
r
u
t
a
r
e
p
m
e
T
I
G
A
1
0
0
0
4
8
S
C
I
I
A
1
0
0
P
O
S
S
T
d
a
e
l
8
e
b
u
t
C
5
8
o
t
C
0
4
-
T
I
G
A
1
0
0
0
4
8
S
C
I
I
A
1
0
0
P
O
S
S
T
d
a
e
l
8
l
e
e
r
&
e
p
a
t
0
0
5
2
C
5
8
o
t
C
0
4
-
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
PDF 
ZIP