Document Outline
- General Description
- Features
- Frequency Select Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- 3.3V Power Supply DC Characteristics
- 2.5V Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise at 62.5MHz @ 3.3V
- Typical Phase Noise at 156.25MHz @ 2.5V
- Parameter Measurement Information
- 3.3V Core/3.3V Output Load AC Test Circuit Diagram
- 3.3V Core/2.5V Output Load AC Test Circuit Diagram
- RMS Phase Jitter Diagram
- Output Skew Diagram
- Output Rise/Fall Time Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Layout Guideline
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
1
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS840002I-01 is a 2 output LVCMOS/LVTTL
Synthesizer optimized to generate Ethernet
reference clock frequencies and is a member of
the HiPerClocks
TM
family of high performance
clock solutions from ICS. Using a 25MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
156.25MHz, 125MHz, and 62.5MHz. The ICS840002I-01 uses
ICS' 3
rd
generation low phase noise VCO technology and can
achieve 1ps or lower typical random rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS840002I-01 is
packaged in a small 16-pin TSSOP package.
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F_SEL0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
F_SEL1
GND
GND
Q0
Q1
V
DDO
XTAL_IN
XTAL_OUT
ICS840002I-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
F
EATURES
Two LVCMOS/LVTTL outputs @ 3.3V,
17
typical output impedance
Selectable crystal oscillator interface
or LVCMOS single-ended input
Supports the following output frequencies:
156.25MHz, 125MHz and 62.5MHz
Output frequency range: 56MHz - 175MHz
VCO range: 560MHz - 700MHz
Output skew: 12ps (maximum)
RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.47ps (typical)
Phase noise:
Offset
Noise Power
100Hz ............... -97.4 dBc/Hz
1KHz .............. -120.2 dBc/Hz
10KHz .............. -127.6 dBc/Hz
100KHz .............. -126.1 dBc/Hz
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40C to 85C ambient operating temperature
Lead-Free package RoHS compliant
Q0
Q1
OE
F_SEL1:0
nPLL_SEL
nXTAL_SEL
XTAL_IN
XTAL_OUT
TEST_CLK
MR
OSC
Phase
Detector
VCO
M = 25 (fixed)
F_SEL1:0
0 0 4
0 1 5
1 0 10
1 1 5
0
1
1
0
2
N
25MHz
Pullup
Pulldown
Pulldown
Pulldown
Pullup:Pullup
Pulldown
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
s
t
u
p
n
I
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
)
.
f
e
R
z
H
M
5
2
(
1
L
E
S
_
F
0
L
E
S
_
F
e
u
l
a
V
r
e
d
i
v
i
D
M
e
u
l
a
V
r
e
d
i
v
i
D
N
0
0
5
2
4
5
2
.
6
5
1
0
1
5
2
5
5
2
1
1
0
5
2
0
1
5
.
2
6
1
1
5
2
5
5
2
1
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
2
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
r
e
b
m
u
N
e
m
a
N
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
6
1
,
1
,
0
L
E
S
_
F
1
L
E
S
_
F
t
u
p
n
I
p
u
ll
u
P
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
n
i
p
t
c
e
l
e
s
y
c
n
e
u
q
e
r
F
2
L
E
S
_
L
A
T
X
n
t
u
p
n
I
n
w
o
d
ll
u
P
e
c
n
e
r
e
f
e
r
L
L
P
e
h
t
s
a
s
t
u
p
n
i
K
L
C
_
T
S
E
T
r
o
l
a
t
s
y
r
c
e
h
t
n
e
e
w
t
e
b
s
t
c
e
l
e
S
L
A
T
X
s
t
c
e
l
e
s
,
W
O
L
n
e
h
W
.
K
L
C
_
T
S
E
T
s
t
c
e
l
e
s
,
H
G
I
H
n
e
h
W
.
e
c
r
u
o
s
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
s
u
p
n
i
3
K
L
C
_
T
S
E
T
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
n
i
k
c
o
l
c
L
T
T
V
L
/
S
O
M
C
V
L
d
e
d
n
e
-
e
l
g
n
i
S
4
E
O
t
u
p
n
I
p
u
ll
u
P
e
h
t
,
W
O
L
n
e
h
W
.
e
v
i
t
c
a
e
r
a
s
t
u
p
t
u
o
e
h
t
,
H
G
I
H
n
e
h
W
.
n
i
p
e
l
b
a
n
e
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
e
t
a
t
s
e
c
n
a
d
e
p
m
i
h
g
i
h
a
n
i
e
r
a
s
t
u
p
t
u
o
5
R
M
t
u
p
n
I
n
w
o
d
ll
u
P
e
r
a
s
r
e
d
i
v
i
d
l
a
n
r
e
t
n
i
e
h
t
,
H
G
I
H
c
i
g
o
l
n
e
h
W
.
t
e
s
e
R
r
e
t
s
a
M
H
G
I
H
e
v
i
t
c
A
l
a
n
r
e
t
n
i
e
h
t
,
W
O
L
c
i
g
o
l
n
e
h
W
.
w
o
l
o
g
o
t
s
t
u
p
t
u
o
e
v
i
t
c
a
g
n
i
s
u
a
c
t
e
s
e
r
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
d
e
l
b
a
n
e
e
r
a
s
t
u
p
t
u
o
e
h
t
d
n
a
s
r
e
d
i
v
i
d
6
L
E
S
_
L
L
P
n
t
u
p
n
I
n
w
o
d
ll
u
P
.
t
u
p
t
u
o
O
C
V
e
h
t
m
o
r
f
n
e
v
i
r
d
s
i
t
u
p
t
u
o
e
h
t
,
W
O
L
n
e
h
W
.
s
s
a
p
y
B
L
L
P
=
y
c
n
e
u
q
e
r
f
t
u
p
t
u
o
e
h
t
d
n
a
d
e
s
s
a
p
y
b
s
i
L
L
P
e
h
t
,
H
G
I
H
n
e
h
W
.
r
e
d
i
v
i
d
t
u
p
t
u
o
N
/
y
c
n
e
u
q
e
r
f
k
c
o
l
c
e
c
n
e
r
e
f
e
r
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
7
V
A
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
g
o
l
a
n
A
8
V
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
e
r
o
C
,
9
0
1
,
T
U
O
_
L
A
T
X
N
I
_
L
A
T
X
t
u
p
n
I
.
e
c
a
f
r
e
t
n
i
r
o
t
a
ll
i
c
s
o
l
a
t
s
y
r
C
1
1
V
O
D
D
r
e
w
o
P
.
n
i
p
y
l
p
p
u
s
t
u
p
t
u
O
3
1
,
2
1
0
Q
,
1
Q
t
u
p
t
u
O
.
s
l
e
v
e
l
e
c
a
f
r
e
t
n
i
L
T
T
V
L
/
S
O
M
C
V
L
.
s
t
u
p
t
u
o
k
c
o
l
c
d
e
d
n
e
-
e
l
g
n
i
S
5
1
,
4
1
D
N
G
r
e
w
o
P
.
d
n
u
o
r
g
y
l
p
p
u
s
r
e
w
o
P
:
E
T
O
N
p
u
ll
u
P
d
n
a
n
w
o
d
ll
u
P
.
s
e
u
l
a
v
l
a
c
i
p
y
t
r
o
f
,
s
c
i
t
s
i
r
e
t
c
a
r
a
h
C
n
i
P
,
2
e
l
b
a
T
e
e
S
.
s
r
o
t
s
i
s
e
r
t
u
p
n
i
l
a
n
r
e
t
n
i
o
t
r
e
f
e
r
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
C
N
I
e
c
n
a
t
i
c
a
p
a
C
t
u
p
n
I
4
F
p
C
D
P
e
c
n
a
t
i
c
a
p
a
C
n
o
i
t
a
p
i
s
s
i
D
r
e
w
o
P
8
F
p
R
P
U
L
L
U
P
r
o
t
s
i
s
e
R
p
u
ll
u
P
t
u
p
n
I
1
5
k
R
N
W
O
D
L
L
U
P
r
o
t
s
i
s
e
R
n
w
o
d
ll
u
P
t
u
p
n
I
1
5
k
R
T
U
O
e
c
n
a
d
e
p
m
I
t
u
p
t
u
O
%
5
V
3
.
3
4
1
7
1
1
2
%
5
V
5
.
2
6
1
1
2
5
2
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
3
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
89C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
7
3
.
2
5
.
2
5
2
6
.
2
V
V
A
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
7
3
.
2
5
.
2
5
2
6
.
2
V
V
O
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
7
3
.
2
5
.
2
5
2
6
.
2
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
5
9
A
m
I
A
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
2
1
A
m
I
O
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
5
A
m
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 3.3V5%
OR
2.5V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
e
r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
g
o
l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
3
1
.
3
3
.
3
5
6
4
.
3
V
5
7
3
.
2
5
.
2
5
2
6
.
2
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
0
0
1
A
m
I
A
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
2
1
A
m
I
O
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
5
A
m
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
4
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
n
o
i
t
a
ll
i
c
s
O
f
o
e
d
o
M
l
a
t
n
e
m
a
d
n
u
F
y
c
n
e
u
q
e
r
F
5
2
z
H
M
)
R
S
E
(
e
c
n
a
t
s
i
s
e
R
s
e
i
r
e
S
t
n
e
l
a
v
i
u
q
E
0
5
e
c
n
a
t
i
c
a
p
a
C
t
n
u
h
S
7
F
p
.
l
a
t
s
y
r
c
t
n
a
n
o
s
e
r
l
e
ll
a
r
a
p
F
p
8
1
n
a
g
n
i
s
u
d
e
z
i
r
e
t
c
a
r
a
h
C
:
E
T
O
N
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
T
U
O
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
0
=
]
0
:
1
[
L
E
S
_
F
0
4
1
5
7
1
z
H
M
1
0
=
]
0
:
1
[
L
E
S
_
F
2
1
1
0
4
1
z
H
M
1
1
r
o
0
1
=
]
0
:
1
[
L
E
S
_
F
6
5
0
7
z
H
M
t
)
o
(
k
s
3
,
1
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
2
1
s
p
t
)
(
t
ij
;
)
m
o
d
n
a
R
(
r
e
t
t
i
J
e
s
a
h
P
S
M
R
2
E
T
O
N
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
z
H
M
5
2
.
6
5
1
7
4
.
0
s
p
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
z
H
M
5
2
1
7
5
.
0
s
p
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
z
H
M
5
.
2
6
1
5
.
0
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
0
2
0
0
7
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
6
4
4
5
%
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
1
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
O
D
D
.
2
/
.
t
o
l
P
e
s
i
o
N
e
s
a
h
P
e
h
t
o
t
r
e
f
e
r
e
s
a
e
l
P
:
2
E
T
O
N
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
3
E
T
O
N
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%
OR
2.5V5%,
OR
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
V
D
D
=
V
3
.
3
2
V
D
D
3
.
0
+
V
V
D
D
V
5
.
2
=
7
.
1
V
D
D
3
.
0
+
V
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
V
D
D
=
V
3
.
3
3
.
0
-
8
.
0
V
V
D
D
V
5
.
2
=
3
.
0
-
7
.
0
V
I
H
I
t
u
p
n
I
t
n
e
r
r
u
C
h
g
i
H
1
L
E
S
_
F
,
0
L
E
S
_
F
,
E
O
V
D
D
V
=
N
I
r
o
V
5
6
4
.
3
=
V
5
2
6
.
2
5
A
,
R
M
,
L
E
S
_
L
L
P
n
K
L
C
_
T
S
E
T
,
L
E
S
_
L
A
T
X
n
V
D
D
V
=
N
I
r
o
V
5
6
4
.
3
=
V
5
2
6
.
2
0
5
1
A
I
L
I
t
u
p
n
I
t
n
e
r
r
u
C
w
o
L
1
L
E
S
_
F
,
0
L
E
S
_
F
,
E
O
V
D
D
,
V
5
2
6
.
2
r
o
V
5
6
4
.
3
=
V
N
I
V
0
=
0
5
1
-
A
,
R
M
,
L
E
S
_
L
L
P
n
K
L
C
_
T
S
E
T
,
L
E
S
_
L
A
T
X
n
V
D
D
,
V
5
2
6
.
2
r
o
V
5
6
4
.
3
=
V
N
I
V
0
=
5
-
A
V
H
O
1
E
T
O
N
;
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
V
O
D
D
%
5
V
3
.
3
=
6
.
2
V
V
O
D
D
%
5
V
5
.
2
=
8
.
1
V
V
L
O
1
E
T
O
N
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
V
O
D
D
%
5
V
5
.
2
r
o
V
3
.
3
=
5
.
0
V
0
5
h
t
i
w
d
e
t
a
n
i
m
r
e
t
s
t
u
p
t
u
O
:
1
E
T
O
N
V
o
t
O
D
D
.
t
i
u
c
r
i
C
t
s
e
T
d
a
o
L
t
u
p
t
u
O
,
n
o
i
t
a
m
r
o
f
n
I
t
n
e
m
e
r
u
s
a
e
M
r
e
t
e
m
a
r
a
P
e
e
S
.
2
/
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
5
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
T
U
O
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
0
=
]
0
:
1
[
L
E
S
_
F
0
4
1
5
7
1
z
H
M
1
0
=
]
0
:
1
[
L
E
S
_
F
2
1
1
0
4
1
z
H
M
1
1
r
o
0
1
=
]
0
:
1
[
L
E
S
_
F
6
5
8
6
z
H
M
t
)
o
(
k
s
3
,
1
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
2
1
s
p
t
)
(
t
ij
;
)
m
o
d
n
a
R
(
r
e
t
t
i
J
e
s
a
h
P
S
M
R
2
E
T
O
N
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
z
H
M
5
2
.
6
5
1
7
4
.
0
s
p
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
z
H
M
5
2
1
5
5
.
0
s
p
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
z
H
M
5
.
2
6
9
4
.
0
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
0
2
0
0
7
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
6
4
4
5
%
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
1
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
O
D
D
.
2
/
.
t
o
l
P
e
s
i
o
N
e
s
a
h
P
e
h
t
o
t
r
e
f
e
r
e
s
a
e
l
P
:
2
E
T
O
N
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
3
E
T
O
N
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
l
a
c
i
p
y
T
m
u
m
i
x
a
M
s
t
i
n
U
f
T
U
O
y
c
n
e
u
q
e
r
F
t
u
p
t
u
O
0
0
=
]
0
:
1
[
L
E
S
_
F
0
4
1
5
7
1
z
H
M
1
0
=
]
0
:
1
[
L
E
S
_
F
2
1
1
0
4
1
z
H
M
1
1
r
o
0
1
=
]
0
:
1
[
L
E
S
_
F
6
5
8
6
z
H
M
t
)
o
(
k
s
3
,
1
E
T
O
N
;
w
e
k
S
t
u
p
t
u
O
2
1
s
p
t
)
(
t
ij
;
)
m
o
d
n
a
R
(
r
e
t
t
i
J
e
s
a
h
P
S
M
R
2
E
T
O
N
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
z
H
M
5
2
.
6
5
1
9
4
.
0
s
p
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
z
H
M
5
2
1
6
5
.
0
s
p
)
z
H
M
0
2
-
z
H
M
5
7
8
.
1
(
z
H
M
5
.
2
6
2
5
.
0
s
p
t
R
t
/
F
e
m
i
T
ll
a
F
/
e
s
i
R
t
u
p
t
u
O
%
0
8
o
t
%
0
2
0
0
2
0
0
7
s
p
c
d
o
e
l
c
y
C
y
t
u
D
t
u
p
t
u
O
6
4
4
5
%
.
s
n
o
i
t
i
d
n
o
c
d
a
o
l
l
a
u
q
e
h
t
i
w
d
n
a
s
e
g
a
t
l
o
v
y
l
p
p
u
s
e
m
a
s
e
h
t
t
a
s
t
u
p
t
u
o
n
e
e
w
t
e
b
w
e
k
s
s
a
d
e
n
i
f
e
D
:
1
E
T
O
N
V
t
a
d
e
r
u
s
a
e
M
O
D
D
.
2
/
.
t
o
l
P
e
s
i
o
N
e
s
a
h
P
e
h
t
o
t
r
e
f
e
r
e
s
a
e
l
P
:
2
E
T
O
N
.
5
6
d
r
a
d
n
a
t
S
C
E
D
E
J
h
t
i
w
e
c
n
a
d
r
o
c
c
a
n
i
d
e
n
i
f
e
d
s
i
r
e
t
e
m
a
r
a
p
s
i
h
T
:
3
E
T
O
N
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
6
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
62.5MH
Z
@3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.51ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
Raw Phase Noise Data
1Gb Ethernet Filter
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
156.25MH
Z
@3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.47ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
Raw Phase Noise Data
10Gb Ethernet Filter
100
1k
10k
100k
1M
10M
100M
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
7
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
Q0, Q1
RMS P
HASE
J
ITTER
O
UTPUT
S
KEW
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
DD
,
V
DDA
, V
DDO
GND
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
O
UTPUT
R
ISE
/F
ALL
T
IME
SCOPE
Qx
LVCMOS
2.05V5%
-1.25V5%
V
DD
,
V
DDA
GND
1.25V5%
V
DDO
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
V
DD
,
V
DDA
, V
DDO
GND
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
8
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS840002I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V or 2.5V
.01
F
V
DD
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS840002I-01 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 25MHz 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
ICS840002I-01
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
9
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
L
AYOUT
G
UIDELINE
Figure 3 shows a schematic example of the ICS840002I-01. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18
pF parallel resonant 25MHz crystal is used. The C1=22pF and
F
IGURE
3. ICS840002I-01 S
CHEMATIC
E
XAMPLE
C2=22pF are recommended for frequency accuracy. For differ-
ent board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. 1K
pullup or pulldown resis-
tors can be used for the logic control input pins.
RU2
Not Install
Logic Control Input Examples
C6
0.1u
Set Logic
Input to
'1'
RD2
1K
VDD
Zo = 50 Ohm
XTAL2
VDD
C3
10uF
X1
To Logic
Input
pins
VDD
R1
10
XTAL1
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
VDD
VDD
R4
100
LVCMOS
Set Logic
Input to
'0'
C4
0.01u
R2
33
Zo = 50 Ohm
VDDA
RU1
1K
U1
ICS840002I-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FSEL0
XTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
VDD
XTAL_OUT
XTAL_IN
VDDO
Q1
Q0
GND
GND
FSEL1
LVCMOS
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
To Logic
Input
pins
RD1
Not Install
C5
0.1u
R3
100
C1
22pF
C2
22pF
Optional Termination
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
10
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS840002I-01 is: 3356
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
16 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
11
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
16 L
EAD
TSSOP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
6
1
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
9
.
4
0
1
.
5
E
C
I
S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
Integrated
Circuit
Systems, Inc.
840002AGI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 3, 2005
12
ICS840002I-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockSTM and F
EMTO
C
LOCKS
TM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
r
e
b
m
u
N
r
e
d
r
O
/
t
r
a
P
g
n
i
k
r
a
M
e
g
a
k
c
a
P
g
n
i
g
a
k
c
a
P
g
n
i
p
p
i
h
S
e
r
u
t
a
r
e
p
m
e
T
1
0
-
I
G
A
2
0
0
0
4
8
S
C
I
1
0
I
A
2
0
0
0
4
8
S
C
I
P
O
S
S
T
d
a
e
L
6
1
e
b
u
t
C
5
8
o
t
C
0
4
-
T
1
0
-
I
G
A
2
0
0
0
4
8
S
C
I
1
0
I
A
2
0
0
0
4
8
S
C
I
P
O
S
S
T
d
a
e
L
6
1
l
e
e
r
&
e
p
a
t
0
0
5
2
C
5
8
o
t
C
0
4
-
F
L
1
0
-
I
G
A
2
0
0
0
4
8
S
C
I
D
B
T
P
O
S
S
T
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
6
1
e
b
u
t
C
5
8
o
t
C
0
4
-
T
F
L
1
0
-
I
G
A
2
0
0
0
4
8
S
C
I
D
B
T
P
O
S
S
T
"
e
e
r
F
-
d
a
e
L
"
d
a
e
L
6
1
l
e
e
r
&
e
p
a
t
0
0
5
2
C
5
8
o
t
C
0
4
-
PDF 
ZIP