Document Outline
- General Description
- Features
- Frequency Select Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- Typical Phase Noise at 62.5MHz @ 3.3V
- Typical Phase Noise at 62.5MHz @ 2.5V
- Typical Phase Noise at 125MHz @ 3.3V
- Typical Phase Noise at 125MHz @ 2.5V
- Typical Phase Noise at 156.25MHz @ 3.3V
- Typical Phase Noise at 156.25MHz @ 2.5V
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input and Output Pins
- Layout Guideline
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
Integrated
Circuit
Systems, Inc.
840004AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
1
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS840004-01 is a 4 output LVCMOS/LVTTL
Synthesizer optimized to generate Ethernet
reference clock frequencies and is a member of
the HiPerClocks
TM
family of high performance
clock solutions from ICS. Using a 25MHz, 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
156.25MHz, 125MHz, and 62.5MHz. The ICS840004-01 uses
ICS' 3
rd
generation low phase noise VCO technology and can
achieve 1ps or lower typical random rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS840004-01 is
packaged in a small 20-pin TSSOP package.
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
F
EATURES
Four LVCMOS/LVTTL outputs,
15
typical output impedance
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Output frequency Range: 56MHz - 175MHz
VCO Range: 560MHz - 700MHz
RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.52ps (typical) design target
Phase noise:
Offset
Noise Power
100Hz ............... -94.9 dBc/Hz
1kHz ............. -119.6 dBc/Hz
10kHz ............. -128.9 dBc/Hz
100kHz ............. -129.2 dBc/Hz
Full 3.3V or 3.3V core/2.5V output supply mode
0C to 70C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
Q0
Q1
Q2
Q3
OE
F_SEL1:0
nPLL_SEL
nXTAL_SEL
XTAL_IN
XTAL_OUT
TEST_CLK
MR
OSC
Phase
Detector
VCO
M = 25 (fixed)
F_SEL1:0
0 0 4
0 1 5
1 0 10
1 1 5
0
1
1
0
2
N
25MHz
Pullup
Pulldown
Pulldown
Pulldown
Pullup:Pullup
Pulldown
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
FOR
E
THERNET
F
REQUENCIES
P
IN
A
SSIGNMENT
ICS840004-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
F_SEL0
nc
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
F_SEL1
GND
Q0
Q1
V
DDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
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Integrated
Circuit
Systems, Inc.
8400042AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
2
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
1. P
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D
ESCRIPTIONS
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Integrated
Circuit
Systems, Inc.
840004AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
3
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DDD
= V
DDA
= 3.3V5%, V
DDO
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
70C
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 3.3V5%
OR
2.5V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4. C
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T
O
N
Integrated
Circuit
Systems, Inc.
8400042AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
4
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
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= 0C
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T
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T
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a
p
s
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h
T
:
3
E
T
O
N
Integrated
Circuit
Systems, Inc.
840004AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
5
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
62.5MH
Z
@3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.55ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
Raw Phase Noise Data
1Gb Ethernet Filter
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
62.5MH
Z
@2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.53ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
1Gb Ethernet Filter to raw data
Raw Phase Noise Data
1Gb Ethernet Filter
100
1k
10k
100k
1M
10M
100M
Integrated
Circuit
Systems, Inc.
8400042AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
6
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
@3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.65ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
Raw Phase Noise Data
10Gb Ethernet Filter
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
@2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.59ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
Raw Phase Noise Data
10Gb Ethernet Filter
100
1k
10k
100k
1M
10M
100M
Integrated
Circuit
Systems, Inc.
840004AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
7
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
156.25MH
Z
@3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.52ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
Raw Phase Noise Data
10Gb Ethernet Filter
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
156.25MH
Z
@2.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.48ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
Raw Phase Noise Data
10Gb Ethernet Filter
100
1k
10k
100k
1M
10M
100M
Integrated
Circuit
Systems, Inc.
8400042AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
8
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
Q0:Q3
RMS P
HASE
J
ITTER
O
UTPUT
S
KEW
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
DD
,
V
DDA
, V
DDO
GND
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
t
sk(o)
V
DDO
2
V
DDO
2
Qx
Qy
O
UTPUT
R
ISE
/F
ALL
T
IME
SCOPE
Qx
LVCMOS
2.05V5%
-1.25V5%
V
DD
,
V
DDA
GND
1.25V5%
V
DDO
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
Integrated
Circuit
Systems, Inc.
840004AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
9
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS840004-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V or 2.5V
.01
F
V
DD
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS840004-01 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown
in
Figure 2
below were determined using a 25MHz 18pF
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
parallel resonant crystal and were chosen to minimize
the ppm error.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
ICS840004-01
Integrated
Circuit
Systems, Inc.
8400042AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
10
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
3.3V
R3
36
RU1
1K
Zo = 50 Ohm
C3
10uF
RD1
Not Install
Logic Control Input Examples
R4
36
R2
10
C6
0.1u
C4
0.01u
To Logic
Input
pins
XTAL_IN
RD2
1K
VDDA
Set Logic
Input to
'1'
LVCMOS
RU2
Not Install
3.3V
3.3V
C5
0.1u
C2
22pF
Set Logic
Input to
'0'
3.3V
Zo = 50 Ohm
LVCMOS
3.3V
To Logic
Input
pins
U1
ICS840004-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
F_SEL0
nc
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
nc
VDD
XTAL_OUT
XTAL_IN
GND
Q3
Q2
VDDO
F_SEL1
GND
Q0
Q1
XTAL_OUT
X1
C1
22pF
L
AYOUT
G
UIDELINE
Figure 3
shows a schematic example of the ICS840004-01. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used. The C1=22pF and
F
IGURE
3. ICS840004-01 S
CHEMATIC
E
XAMPLE
C2=22pF are recommended for frequency accuracy. For dif-
ferent board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy. 1K
pullup or pulldown
resistors can be used for the logic control input pins.
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
TEST_CLK I
NPUT
:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the TEST_CLK to
ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
Integrated
Circuit
Systems, Inc.
840004AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
11
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS840004-01 is: 3085
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Integrated
Circuit
Systems, Inc.
8400042AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
12
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
N
I
M
X
A
M
N
0
2
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
4
.
6
0
6
.
6
E
C
I
S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
Reference Document: JEDEC Publication 95, MO-153
Integrated
Circuit
Systems, Inc.
840004AG-01
www.icst.com/products/hiperclocks.html
REV. B JANUARY 3, 2006
13
ICS840004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and F
EMTO
C
LOCKS
are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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