Document Outline
- General Description
- Features
- Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- AC Characteristics
- Typical Phase Noise at 106.25MHz
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- RMS Phase Jitter Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Application Schematic
- Schematic Example
- PC Board Layout Example
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
1
Integrated
Circuit
Systems, Inc.
ICS840011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS840011 is a Fibre Channel Clock
Generator and a member of the HiPerClocks
TM
family of high performance devices from ICS.
The ICS840011 uses a 26.5625MHz or 25MHz
crystal to synthesize 106.25MHz or 100MHz
respectively. The ICS840011 has excellent phase jitter
performance, from 637KHz 10MHz integration range. The
ICS840011 is packaged in a small 8-pin TSSOP, making it
ideal for use in systems with limited board space.
F
EATURES
1 LVCMOS/LVTTL output, 7 output impedence
Crystal oscillator interface designed for a 26.5625MHz or
25MHz, 18pF parallel resonant crystal
Output frequency: 106.25MHz (typical)
VCO range: 560MHz to 680MHz
RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637KHz - 10MHz): 0.780ps (typical)
RMS phase noise at 106.25MHz (typical)
Phase noise:
Offset
Noise Power
100Hz ............... -95.7 dBc/Hz
1KHz ................ -121 dBc/Hz
10KHz ................ -129 dBc/Hz
100KHz .............. -129.6 dBc/Hz
3.3V operating supply
-30C to 85C ambient operating temperature
HiPerClockSTM
ICS
ICS840011
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
V
DDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
V
DD
Q0
GND
nc
8
7
6
5
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
OSC
Phase
Detector
VCO
637.5MHz w/
26.5625MHz Ref.
M = 24 (fixed)
6
XTAL_IN
XTAL_OUT
OE
Q0
F
REQUENCY
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(Pullup)
840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
2
Integrated
Circuit
Systems, Inc.
ICS840011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
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840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
3
Integrated
Circuit
Systems, Inc.
ICS840011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= -30C
TO
85C
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5. C
RYSTAL
C
HARACTERISTICS
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= -30C
TO
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840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
4
Integrated
Circuit
Systems, Inc.
ICS840011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
YPICAL
P
HASE
N
OISE
AT
106.25MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
106.25MHz
RMS Phase Jitter (Random)
637K to 10MHz = 0.780ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
Fibre Channel Filter
840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
5
Integrated
Circuit
Systems, Inc.
ICS840011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V 5%
-1.65V 5%
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
Q0
GND
V
DD
RMS P
HASE
J
ITTER
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
6
Integrated
Circuit
Systems, Inc.
ICS840011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS840011 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 26.5625MHz, 18pF
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS840011 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V
DD
, and V
DDA
should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required.
Figure 1
illustrates how a 10
resistor along with a 10F and a .01F
bypass capacitor should be connected to each V
DDA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
7
Integrated
Circuit
Systems, Inc.
ICS840011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
A
PPLICATION
S
CHEMATIC
Figure 3A shows a schematic example of the ICS840011. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18pF
parallel resonant 26.5625MHz crystal is used for generating
106.25MHz output frequency. The C1 = 27pF and C2 = 33pF
are recommended for frequency accuracy. For different board
layout, the C1 and C2 values may be slightly adjusted for opti-
mizing frequency accuracy.
F
IGURE
3A. ICS840011 S
CHEMATIC
E
XAMPLE
PC B
OARD
L
AYOUT
E
XAMPLE
Figure 3B shows an example of P.C. board layout. The crystal
X1 footprint in this example allows either surface mount (HC49S)
or through hole (HC49) package. C3 is 0805. C1 and C2 are
0402. Other resistors and capacitors are 0603. This layout as-
sumes that the board has clean analog power and ground planes.
F
IGURE
3B. ICS840011 PC B
OARD
L
AYOUT
E
XAMPLE
R3
43
Zo = 50 Ohm
R2
10
OE
C5
0.1u
VDD
U1
ICS840011
1
2
3
4
8
7
6
5
VDDA
OE
XTAL_OUT
XTAL_IN
VDD
Q0
GND
NC
C4
0.1u
C3
10uF
C1
27pF
C2
33pF
VDD=3.3V
X1
VDDA
VDD
Q
LVCMOS
840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
8
Integrated
Circuit
Systems, Inc.
ICS840011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS840011 is: 1521
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters Per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
9
Integrated
Circuit
Systems, Inc.
ICS840011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
10
Integrated
Circuit
Systems, Inc.
ICS840011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
840011AG
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 15, 2004
11
Integrated
Circuit
Systems, Inc.
ICS840011
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
E
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PDF 
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