Document Outline
- General Description
- Features
- Frequency Select Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- 3.3V Power Supply DC Characteristics
- 3.3V/2.5V Power Supply DC Characteristics
- 2.5V Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise at 53.125MHz
- Typical Phase Noise at 106.25MHz
- Parameter Measurement Information
- 3.3V Core/3.3V Output Load AC Test Circuit Diagram
- 3.3V Core/2.5V Output Load AC Test Circuit Diagram
- 2.5V Core/2.5V Output Load AC Test Circuit Diagram
- RMS Phase Jitter Diagram
- Output Skew Diagram
- Output Rise/Fall Time Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Layout Guideline
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
Integrated
Circuit
Systems, Inc.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
1
ICS840014I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS840014I is a 4 output LVCMOS/LVTTL
Synthesizer optimized to generate Fibre Channel
reference clock frequencies and is a member of
the HiPerClocks
TM
family of high performance
clock solutions from ICS. This device uses a
26.5625MHz, 18pF parallel resonant crystal to synthesize
106.25MHz. Using FemtoClock's
TM
ultra-low phase noise VCO
technology, the ICS840014I can achieve 1ps or lower typical
random rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS840014I is packaged in a small 20-pin
TSSOP package.
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
F
EATURES
Four LVCMOS/LVTTL outputs, 15
typical output impedance
Selectable crystal oscillator interface
or LVCMOS single-ended input
Output frequency: 106.25MHz or 53.125MHz
RMS phase jitter @ 106.25MHz (637KHz - 5MHz):
0.72ps (typical)
Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40C to 85C ambient operating temperature
Q0
Q1
Q2
Q3
OE
F_SEL
nPLL_SEL
nXTAL_SEL
XTAL_IN
XTAL_OUT
TEST_CLK
MR
OSC
Phase
Detector
VCO
M = 24 (fixed)
F_SEL
0 6
1 12
0
1
1
0
26.5625MHz
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
P
IN
A
SSIGNMENT
ICS840014I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
F_SEL
nc
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
GND
Q0
Q1
V
DDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
Pullup
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
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5
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
Integrated
Circuit
Systems, Inc.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
2
ICS840014I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
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ABLE
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1
Integrated
Circuit
Systems, Inc.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
3
ICS840014I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DDD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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S
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DC C
HARACTERISTICS
,
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DD
= V
DDA
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DDO
= 2.5V5%, T
A
= -40C
TO
85C
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r
u
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y
l
p
p
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t
u
p
t
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O
4
A
m
T
ABLE
3C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
l
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p
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t
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p
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u
O
4
A
m
Integrated
Circuit
Systems, Inc.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
4
ICS840014I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
r
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t
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m
a
r
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P
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:
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T
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3D. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 3.3V5%
OR
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TO
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%
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=
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8
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h
t
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m
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a
P
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e
S
.
2
/
Integrated
Circuit
Systems, Inc.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
5
ICS840014I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
l
o
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m
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S
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HARACTERISTICS
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TO
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t
e
m
a
r
a
p
s
i
h
T
:
3
E
T
O
N
Integrated
Circuit
Systems, Inc.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
6
ICS840014I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
53.125MH
Z
(3.3V)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
53.125MHz
RMS Phase Jitter (Random)
637KHz to 5MHz = 0.63ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
Fibre ChannelFilter Filter
T
YPICAL
P
HASE
N
OISE
AT
106.25MH
Z
(3.3V)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
106.25MHz
RMS Phase Jitter (Random)
637KHz to 5MHz = 0.75ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
Fibre ChannelFilter
Integrated
Circuit
Systems, Inc.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
7
ICS840014I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
Q0:Q3
RMS P
HASE
J
ITTER
O
UTPUT
S
KEW
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
DD
,
V
DDA
, V
DDO
GND
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
O
UTPUT
R
ISE
/F
ALL
T
IME
SCOPE
Qx
LVCMOS
2.05V5%
-1.25V5%
V
DD
,
V
DDA
GND
1.25V5%
V
DDO
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
V
DD
,
V
DDA
, V
DDO
GND
Integrated
Circuit
Systems, Inc.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
8
ICS840014I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS840014I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS840014I has been characterized with 18pF parallel reso-
nant crystals. The capacitor values shown in
Figure 2 below were
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
determined using a 26.5625MHz 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
ICS840014I
Integrated
Circuit
Systems, Inc.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
9
ICS840014I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS840014I is: 3085
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
L
AYOUT
G
UIDELINE
Figure 3 shows a schematic example of the ICS840014I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in
the LVCMOS Termination Application Note. In this example,
an 18pF parallel resonant 26.5625MHz crystal is used. The
F
IGURE
3. ICS840014I S
CHEMATIC
E
XAMPLE
C1=22pF and C2=22pF are recommended for frequency ac-
curacy. For different board layout, the C1 and C2 may be
slightly adjusted for optimizing frequency accuracy. 1K
pullup or pulldown resistors can be used for the logic control
input pins.
C1
22pF
Logic Control Input Examples
RU2
Not Install
3.3V
Set Logic
Input to
'1'
3.3V
C4
0.01u
To Logic
Input
pins
C5
0.1u
U1
ICS840014
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
F_SEL
nc
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
nc
VDD
XTAL_OUT
XTAL_IN
GND
Q3
Q2
VDDO
nc
GND
Q0
Q1
R4
36
C2
22pF
Zo = 50 Ohm
LVCMOS
3.3V
C6
0.1u
R3
36
VDDA
XTAL_OUT
3.3V
RD1
Not Install
C3
10uF
RU1
1K
RD2
1K
Zo = 50 Ohm
To Logic
Input
pins
LVCMOS
R2
10
3.3V
X1
XTAL_IN
Set Logic
Input to
'0'
ICS80014I
Integrated
Circuit
Systems, Inc.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
10
ICS840014I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
N
I
M
X
A
M
N
0
2
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
4
.
6
0
6
.
6
E
C
I
S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
Reference Document: JEDEC Publication 95, MO-153
Integrated
Circuit
Systems, Inc.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
11
ICS840014I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockSTM and F
EMTO
C
LOCKS
TM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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