Document Outline
- General Description
- Features
- Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Conrol Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- AC Characterisitcs
- Typical Phase Noise Plot at 62.5MHz
- Typical Phase Noise Plot at 125MHz
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- RMS Phase Jitter Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Application Schematic
- Schematic Example
- PC Board Layout Example
- Footprint Table
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
840022AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 11, 2005
1
Integrated
Circuit
Systems, Inc.
ICS840022
F
EMTO
C
LOCKS
TMC
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS840022 is a Gigabit Ethernet Clock
Generator and a member of the HiPerClocks
TM
family of high performance devices from ICS.
The ICS840022 uses a 25MHz crystal to
synthesize 125MHz or 62.5MHz. The ICS840022
has excellent phase jitter performance, over the 1.875MHz
20MHz integration range. The ICS840022 is packaged in a
small 8-pin TSSOP, making it ideal for use in systems with
limited board space.
F
EATURES
1 LVCMOS/LVTTL output, 7 output impedence
Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
Output frequencies: 125MHz or 62.5MHz (selectable)
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.55ps (typical)
RMS phase noise at 125MHz:
Offset
Noise Power
100Hz .............. -106.3 dBc/Hz
1KHz .............. -126.3 dBc/Hz
10KHz .............. -131.7 dBc/Hz
100KHz .............. -130.8 dBc/Hz
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
ICS
ICS840022
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
V
DDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
V
DD
Q0
GND
FREQ_SEL
8
7
6
5
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
OSC
Phase
Detector
VCO
560MHz-680MHz
w/25MHz Ref.
M = 25 (fixed)
0
1
10
5
XTAL_IN
XTAL_OUT
OE
FREQ_SEL
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F
UNCTION
T
ABLE
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840022AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 11, 2005
2
Integrated
Circuit
Systems, Inc.
ICS840022
F
EMTO
C
LOCKS
TMC
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
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ABLE
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840022AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 11, 2005
3
Integrated
Circuit
Systems, Inc.
ICS840022
F
EMTO
C
LOCKS
TMC
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
70C
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5. C
RYSTAL
C
HARACTERISTICS
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
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840022AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 11, 2005
4
Integrated
Circuit
Systems, Inc.
ICS840022
F
EMTO
C
LOCKS
TMC
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
AT
62.5MH
Z
(3.3V)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.55ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
Gb Ethernet Filter to raw data
Raw Phase Noise Data
Gb Ethernet Filter
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
(3.3V)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.50ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
Gb Ethernet Filter to raw data
Raw Phase Noise Data
Gb Ethernet Filter
840022AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 11, 2005
5
Integrated
Circuit
Systems, Inc.
ICS840022
F
EMTO
C
LOCKS
TMC
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V 5%
-1.65V 5%
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
Q0
GND
V
DD
RMS P
HASE
J
ITTER
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
840022AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 11, 2005
6
Integrated
Circuit
Systems, Inc.
ICS840022
F
EMTO
C
LOCKS
TMC
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
A
PPLICATION
I
NFORMATION
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS840022 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS840022 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V
DD
, and V
DDA
should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required.
Figure 1
illustrates how a 10
resistor along with a 10F and a .01F
bypass capacitor should be connected to each V
DDA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
C1
33p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
840022AG
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REV. A JANUARY 11, 2005
7
Integrated
Circuit
Systems, Inc.
ICS840022
F
EMTO
C
LOCKS
TMC
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
A
PPLICATION
S
CHEMATIC
Figure 3A shows a schematic example of the ICS840022. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18pF
parallel resonant 25MHz crystal is used for generating 125MHz
output frequency. The C1 = 22pF and C2pF = 33pF are recom-
mended for frequency accuracy. For different board layout, the
C1 and C2 values may be slightly adjusted for optimizing fre-
quency accuracy.
F
IGURE
3A. ICS840022 S
CHEMATIC
E
XAMPLE
F
IGURE
3B. ICS840022 PC B
OARD
L
AYOUT
E
XAMPLE
PC B
OARD
L
AYOUT
E
XAMPLE
Figure 3B shows an example of ICS840022 P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age. The footprints of other components in this example are listed
in the
Table 7. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
T
ABLE
7. F
OOTPRINT
T
ABLE
e
c
n
e
r
e
f
e
R
e
z
i
S
2
C
,
1
C
2
0
4
0
3
C
5
0
8
0
5
C
,
4
C
3
0
6
0
3
R
,
2
R
,
1
R
3
0
6
0
t
n
e
n
o
p
m
o
c
s
t
s
il
,
7
e
l
b
a
T
:
E
T
O
N
.
e
l
p
m
a
x
e
t
u
o
y
a
l
s
i
h
t
n
i
n
w
o
h
s
s
e
z
i
s
C1
22pF
LVCMOS
VDDA
U1
ICS840022
1
2
3
4
8
7
6
5
VDDA
OE
XTAL_OUT
XTAL_IN
VDD
Q0
GND
FREQ_SEL
VDD
FRE_SEL
R2
10
VDD=3.3V
VDD
C4
0.1u
Q
X1
OE
R1
1K
C2
33pF
VDD
R3
33
C3
10uF
Zo = 50 Ohm
C5
0.1u
840022AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 11, 2005
8
Integrated
Circuit
Systems, Inc.
ICS840022
F
EMTO
C
LOCKS
TMC
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS840022 is: 1984
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
840022AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 11, 2005
9
Integrated
Circuit
Systems, Inc.
ICS840022
F
EMTO
C
LOCKS
TMC
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
8
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
9
.
2
0
1
.
3
E
C
I
S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
840022AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 11, 2005
10
Integrated
Circuit
Systems, Inc.
ICS840022
F
EMTO
C
LOCKS
TMC
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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C
0
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t
C
0
The aforementioned trademarks, HiPerClockSTM and F
EMTO
C
LOCKS
TM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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