Document Outline
- General Description
- Features
- Frequency Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Control Function Table
- FREQ_SEL Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- AC Characterisitcs
- Typical Phase Noise Plot at 156.25MHz
- Typical Phase Noise Plot at 75MHz
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- RMS Phase Jitter Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
840051AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 14, 2005
1
Integrated
Circuit
Systems, Inc.
ICS840051
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS840051 is a Gigabit Ethernet Clock
Generator and a member of the HiPerClocks
TM
family of high performance devices from ICS.
The ICS840051 can synthesize 10 Gigabit
Ethernet, SONET, or Serial ATA reference clock
frequencies with the appropriate choice of crystal and
output divider. The ICS840051 has excellent phase jitter
performance and is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
F
EATURES
1 LVCMOS/LVTTL output, 15 output impedance
Crystal oscillator interface designed for
18pF parallel resonant crystals
Output frequency range: 70MHz - 170MHz
VCO range: 560MHz - 680MHz
RMS phase jitter at 155.52MHz (1.875MHz - 20MHz):
0.48ps (typical)
RMS phase noise at 155.52MHz
Offset Noise Power
100Hz ............... -99.7 dBc/Hz
1KHz ................ -120 dBc/Hz
10KHz ................ -128 dBc/Hz
100KHz ................ -127 dBc/Hz
3.3V operating supply
0C to 70C ambient operating temperature
Lead-Free fully RoHS compliant
Industrial temperature information available upon request
HiPerClockSTM
ICS
ICS840051
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
V
DDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
V
DD
Q0
GND
FREQ_SEL
8
7
6
5
B
LOCK
D
IAGRAM
OSC
Phase
Detector
VCO
560MHz-680MHz
0 4 (default)
1 8
32
(fixed)
XTAL_IN
XTAL_OUT
Q0
F
REQUENCY
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Pullup
Pulldown
840051AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 14, 2005
2
Integrated
Circuit
Systems, Inc.
ICS840051
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
2. P
IN
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HARACTERISTICS
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840051AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 14, 2005
3
Integrated
Circuit
Systems, Inc.
ICS840051
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
70C
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5. C
RYSTAL
C
HARACTERISTICS
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
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DD
= V
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840051AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 14, 2005
4
Integrated
Circuit
Systems, Inc.
ICS840051
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
6. AC C
HARACTERISTICS
,
V
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= V
DDA
= 3.3V5%, T
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TO
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840051AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 14, 2005
5
Integrated
Circuit
Systems, Inc.
ICS840051
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
YPICAL
P
HASE
N
OISE
AT
155.52MH
Z
0
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-170
-180
-190
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
10GigE Filter to raw data
Raw Phase Noise Data
10GigE Filter
155.52MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.48ps (typical)
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
77.76MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
10GigE Filter to raw data
Raw Phase Noise Data
10GigE Filter
77.76MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.45ps (typical)
100
1k
10k
100k
1M
10M
100M
840051AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 14, 2005
6
Integrated
Circuit
Systems, Inc.
ICS840051
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V 5%
-1.65V 5%
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
Q0
GND
V
DD
RMS P
HASE
J
ITTER
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
840051AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 14, 2005
7
Integrated
Circuit
Systems, Inc.
ICS840051
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS840051 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using an 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS840051 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V
DD
and V
DDA
should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required.
Figure 1
illustrates how a 10
resistor along with a 10F and a .01F
bypass capacitor should be connected to each V
DDA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
C1
33p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
840051AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 14, 2005
8
Integrated
Circuit
Systems, Inc.
ICS840051
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS840051 is: 1927
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
840051AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 14, 2005
9
Integrated
Circuit
Systems, Inc.
ICS840051
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
8
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
9
.
2
0
1
.
3
E
C
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S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
840051AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 14, 2005
10
Integrated
Circuit
Systems, Inc.
ICS840051
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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