Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Functional Description
- Parallel & Serial Load Operations Diagram
- Pin Descriptions
- Pin Characteristics
- Parallel & Serial Mode Function Table
- Programmable VCO Frequency Function Table
- Programmable Output Divider Function Table
- Commonly Used Configuration Function Table
- Output Enable & Clock Enable Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Input Frequency Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 3.3V/1.8V AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 3.3V/2.5V Output Load AC Test Circuit Diagram
- 3.3V/1.8V Output Load AC Test Circuit Diagram
- Period Jitter Diagram
- Output Skew Diagram
- Output Rise/Fall Time Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
1
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS84021 is a general purpose, Crystal-to-
LVCMOS/LVTTL High Frequency Synthesizer
and a member of the HiPerClockSTM family of
High Performance Clock Solutions from ICS. The
ICS84021 has a selectable TEST_CLK or crys-
tal input. The VCO operates at a frequency range of 620MHz
to 780MHz. The VCO frequency is programmed in steps
equal to the value of the input reference or crystal frequency.
The VCO and output frequency can be programmed using
the serial or parallel interface to the configuration logic. The
low phase noise characteristics of the ICS84021 make it an
ideal clock source for Gigabit Ethernet, SONET, Fibre Chan-
nel 1 and 2, and Infiniband applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
2 LVCMOS/LVTTL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
Output frequency range: 103.3MHz to 260MHz
Crystal input frequency range: 14MHz to 40MHz
VCO range: 620MHz to 780MHz
Parallel or serial interface for programming counter
and output dividers
RMS period jitter: 4.3ps (typical) (N 4, V
DDO
= 3.3V 5%)
RMS phase jitter at 155.52MHz, using a 38.88MHz crystal
(12KHz to 20MHz): 2.88ps (typical)
Phase noise: 155.52MHz
Offset
Noise Power
100Hz ................. -93.7 dBc/Hz
1KHz ............... -111.3 dBc/Hz
10KHz ............... -120.4 dBc/Hz
100KHz ............... -125.1 dBc/Hz
Full 3.3V or mixed 3.3V core/2.5V or 1.8V supply voltage
0C to 70C ambient operating temperature
Industrial temperature information available upon request
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL2
TEST_CLK
XTAL_SEL
V
DDA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N0
N1
nc
GND
GND
Q0
Q1
V
DDO
OE0
OE1
V
DD
TEST
X
T
AL1
nP_LO
A
D
VCO_SEL
M0
M1
M2
M3
M4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS84021
HiPerClockSTM
ICS
OSC
OE0
OE1
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL1
XTAL2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
Q0
Q1
TEST
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
PHASE DETECTOR
3
4
5
6
MR
84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
2
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
M divider and N output divider to a specific default state that will
automatically occur during power-up. The TEST output is LOW
when operating in the parallel input mode. The relationship be-
tween the VCO frequency, the crystal frequency and the M di-
vider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 25
M 31. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by sampling
the S_DATA bits with the rising edge of S_CLOCK. The con-
tents of the shift register are loaded into the M divider and N
output divider when S_LOAD transitions from LOW-to-HIGH.
The M divide and N output divide values are latched on the
HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,
data at the S_DATA input is passed directly to the M divider
and N output divider on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and
test bits T1 and T0. The internal registers T0 and T1 deter-
mine the state of the TEST output as follows:
F
UNCTIONAL
D
ESCRIPTION
fVCO = fxtal x M
T1
T0
TEST Output
0
0
LOW
0
1
S_DATA, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE: The NULL timing slot must be observed.
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
T 1
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M 0
FOUT = fVCO = fxtal x M
N
N
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the
Input Frequency Characteristics, Table 5, NOTE 1.
The ICS84021 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 620MHz to 780MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of
the LVCMOS output buffers. The divider provides a 50% out-
put duty cycle.
The programmable features of the ICS84021 support two input
modes to program the M divider and N output divider. The two
input operational modes are parallel and serial.
Figure 1 shows
the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 and N0 and N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the nP_LOAD
input, the data is latched and the M divider remains loaded until
the next LOW transition on nP_LOAD or until a serial event oc-
curs. As a result, the M and N bits can be hardwired to set the
84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
3
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
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84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
4
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
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3B. P
ROGRAMMABLE
VCO F
REQUENCY
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UNCTION
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(NOTE 1)
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84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
5
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
(PLL E
NABLED
)
T
ABLE
3E. O
UTPUT
E
NABLE
& C
LOCK
E
NABLE
F
UNCTION
T
ABLE
s
t
u
p
n
I
l
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n
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C
t
u
p
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0
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1
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1
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-
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b
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E
T
ABLE
3D. C
OMMONLY
U
SED
C
ONFIGURATION
F
UNCTION
T
ABLE
t
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)
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H
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(
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3
1
84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
6
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
=V
DDA
=3.3V5%, V
DDO
=3.3V5%, 2.5V5%
OR
1.8V5%, T
A
=0C
TO
70C
l
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b
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w
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0
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m
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l
p
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a
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5
2
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D
D
t
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l
p
p
u
S
t
u
p
t
u
O
5
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
7
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
=V
DDA
=3.3V5%,
V
DDO
=3.3V5%, 2.5V5%
OR
1.8V5%, T
A
=0C
TO
70C
l
o
b
m
y
S
r
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t
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m
a
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P
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:
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+
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V
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=
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5
6
4
.
3
=
0
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1
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,
1
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,
0
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,
5
M
L
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V
,
L
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A
T
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V
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=
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I
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5
6
4
.
3
=
5
A
I
L
I
t
u
p
n
I
t
n
e
r
r
u
C
w
o
L
,
R
M
,
1
N
,
0
N
,
8
M
-
6
M
,
4
M
-
0
M
,
K
L
C
_
T
S
E
T
,
K
C
O
L
C
_
S
D
A
O
L
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P
n
,
D
A
O
L
_
S
,
A
T
A
D
_
S
V
D
D
,
V
5
6
4
.
3
=
V
N
I
V
0
=
5
-
A
,
1
E
O
,
0
E
O
,
5
M
L
E
S
_
O
C
V
,
L
E
S
_
L
A
T
X
V
D
D
,
V
5
6
4
.
3
=
V
N
I
V
0
=
0
5
1
-
A
V
H
O
1
E
T
O
N
;
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
V
O
D
D
%
5
V
3
.
3
=
6
.
2
V
V
O
D
D
%
5
V
5
.
2
=
8
.
1
V
V
O
D
D
%
5
V
8
.
1
=
V
O
D
D
3
.
0
-
V
V
L
O
1
E
T
O
N
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
V
O
D
D
%
5
V
3
.
3
=
5
.
0
V
V
O
D
D
%
5
V
5
.
2
=
5
.
0
V
V
O
D
D
%
5
V
8
.
1
=
4
.
0
V
NOTE 1: Outputs terminated with 50
to V
DDO
/2. See
Parameter Measurement Section, "Load Test Circuit Diagrams".
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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t
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m
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r
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P
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p
n
I
1
E
T
O
N
;
K
L
C
_
T
S
E
T
4
1
0
4
z
H
M
1
E
T
O
N
;
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L
A
T
X
,
1
L
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T
X
4
1
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4
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d
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h
t
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F
:
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T
O
N
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4
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r
a
M
f
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s
e
u
l
a
v
d
il
a
v
,
z
H
M
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1
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g
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a
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M
0
8
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M
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6
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h
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M
.
5
5
6
1
e
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a
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H
M
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4
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m
u
m
i
x
a
m
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h
t
g
n
i
s
U
M
.
9
1
T
ABLE
6. C
RYSTAL
C
HARACTERISTICS
r
e
t
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m
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P
s
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F
y
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q
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F
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1
0
4
z
H
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S
E
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l
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5
C
(
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c
n
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t
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c
a
p
a
C
t
n
u
h
S
O
)
7
F
p
84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
8
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
l
o
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5
6
d
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p
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:
3
E
T
O
N
T
ABLE
7B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= 0C
TO
70C
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.
5
6
d
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:
3
E
T
O
N
T
ABLE
7A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
9
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
7C. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V5%, T
A
= 0C
TO
70C
l
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b
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84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
10
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
V
DD
, V
DDA
, V
DDO
= 1.65V5%
GND
= -1.65V5%
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ERIOD
J
ITTER
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
Q0, Q1
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
SCOPE
Qx
LVCMOS
2.05V5%
GND
= -1.25V5%
V
DD
,
V
DDA
V
DDO
1.25V5%
O
UTPUT
S
KEW
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
SCOPE
Qx
LVCMOS
2.4V5%
GND
= -0.9V5%
V
DD
,
V
DDA
V
DDO
0.9V5%
84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
11
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS84021 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in
Figure 3 below were determined using a 25MHz, 18pF
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84021 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 24
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
pin.
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
24
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
C1
22p
X1
18pF Parallel Cry stal
C2
22p
XTAL2
XTAL1
84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
12
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS84021 is: 4325
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
13
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
O
I
T
A
I
R
A
V
C
E
D
E
J
S
R
E
T
E
M
I
L
L
I
M
N
I
S
N
O
I
S
N
E
M
I
D
L
L
A
L
O
B
M
Y
S
A
B
B
M
U
M
I
N
I
M
L
A
N
I
M
O
N
M
U
M
I
X
A
M
N
2
3
A
-
-
-
-
0
6
.
1
1
A
5
0
.
0
-
-
5
1
.
0
2
A
5
3
.
1
0
4
.
1
5
4
.
1
b
0
3
.
0
7
3
.
0
5
4
.
0
c
9
0
.
0
-
-
0
2
.
0
D
C
I
S
A
B
0
0
.
9
1
D
C
I
S
A
B
0
0
.
7
2
D
.
f
e
R
0
6
.
5
E
C
I
S
A
B
0
0
.
9
1
E
C
I
S
A
B
0
0
.
7
2
E
.
f
e
R
0
6
.
5
e
C
I
S
A
B
0
8
.
0
L
5
4
.
0
0
6
.
0
5
7
.
0
0
-
-
7
c
c
c
-
-
-
-
0
1
.
0
84021AY
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 7, 2003
14
Integrated
Circuit
Systems, Inc.
ICS84021
260MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
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