Document Outline
- General Description
- Features
- Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 3.3V/1.8V AC Characteristics
- Typical Phase Noise Plot
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 3.3V/2.5V Output Load AC Test Circuit Diagram
- 3.3V/1.8V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- Cycle-to-Cycle Jitter Diagram
- Period Jitter Diagram
- odc, tPW & tPeriod Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Power Supply Filtering Techniques w/Diagram
- Crystal Input Interface w/Diagram
- Schematic Example
- Power & Grounding
- Clock Traces & Termination
- Crystal
- PCB Board Layout
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
1
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS84025 is a Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer with Fanout Buffer and
a member of the HiPerClockSTM family of High
Performance Clock Solutions from ICS. The
VCO frequency is programmed in steps equal
to the value of the crystal frequency. The VCO and
output frequency can be programmed using the feedback and
output frequency select pins. The low phase noise character-
istics of the ICS84025 make it an ideal clock source for Fibre
Channel 1 and Gigabit Ethernet applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
6 LVCMOS/LVTTL outputs
Crystal oscillator interface
Output frequency range: 53.125MHz to 125MHz
Crystal input frequency: 25MHz and 25.5MHz
RMS phase jitter at 106.25, using a 25.5MHz crystal
(637KHz to 10MHz): 3.25ps
Phase noise:
Offset
Noise Power
100Hz ................. -100 dBc/Hz
1KHz ................. -115 dBc/Hz
10KHz ................. -125 dBc/Hz
100KHz ................. -127 dBc/Hz
3.3V core, outputs may either be 3.3V, 2.5V or 1.8V
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
Q0:Q5
PLL
6
/
Feedback
Divider
OSC
Output
Divider
0
1
XTAL1
XTAL2
F_SEL1
PLL_SEL
MR
F_SEL0
ICS84025
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
V
DDO
Q0
GND
Q1
V
DDO
Q2
GND
Q3
V
DDO
Q4
GND
Q5
1
2
3
4
5
6
7
8
9
10
11
12
F_SEL0
F_SEL1
MR
XTAL1
XTAL2
GND
V
DDA
V
DD
PLL_SEL
GND
nc
V
DDO
24
23
22
21
20
19
18
17
16
15
14
13
F
UNCTION
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ABLE
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M
5
2
1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
2
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
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84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
3
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
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DD
= V
DDA
= 3.3V 5%, T
A
= 0C
TO
70C
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
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3
.
3
=
5
.
0
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2
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8
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
46.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
r
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p
84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
4
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V 5%, V
DDO
= 1.8V 0.15V, T
A
= 0C
TO
70C
l
o
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T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V 5%, T
A
= 0C
TO
70C
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V 5%, V
DDO
= 2.5V 5%, T
A
= 0C
TO
70C
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V
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.
s
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.
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6
d
r
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d
n
a
t
S
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84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
5
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
T
YPICAL
P
HASE
N
OISE
25MHz Input
RMS Phase Noise Jitter
12K to 20MHz = 3.5ps (typical)
125MHz
62.5MHz
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
10
100
1k
10k
100k
1M
10M
O
FFSET
F
REQUENCY
(H
Z
)
P
HASE
N
OISE
(
dBc
)
H
Z
O
FFSET
F
REQUENCY
(H
Z
)
P
HASE
N
OISE
(
dBc
)
H
Z
25.5MHz Input
RMS Phase Noise Jitter
12K to 20MHz = 3.5ps (typical)
106.25MHz
53.125MHz
10
100
1k
10k
100k
1M
10M
84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
6
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
SCOPE
Qx
LVCMOS
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
3.3V/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
odc, t
PW
& t
P
ERIOD
SCOPE
Qx
LVCMOS
2.05V5%
V
DDO
GND =
-1.25V5%
V
DD
1.25V5%
SCOPE
Qx
LVCMOS
V
DD
, V
DDA
,
V
DDO
= 1.65V5%
GND = -1.65V5%
tsk(o)
V
DDO
2
V
DDO
2
Qy
Qx
Q0:Q5
V
DDO
2
V
DDO
2
V
DDO
2
Cycle-to-Cycle Jitter
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
Period Jitter
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
Q0:Q5
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock Outputs
20%
80%
80%
20%
t
R
t
F
P
ARAMETER
M
EASUREMENT
I
NFORMATION
GND = -0.9V0.075V
V
DDO
V
DD
2.4 0.9V
0.9V0.075V
84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
7
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84025 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 24
resistor along with a 10
F and a .01
F bypass
capacitor should be connected to each V
DDA
pin.
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
24
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
A crystal can be characterized for either series or parallel
mode operation. The ICS84025 has a built-in crystal oscillator
circuit. This interface can accept either a series or parallel
crystal without additional components and generate
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
frequencies with accuracy suitable for most applications.
Additional accuracy can be achieved by adding two small
capacitors C1 and C2 as shown in
Figure 3.
C2
22pF
C1
18pF
25MHz X1
ICS84025
20
21
XTAL2
XTAL1
84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
8
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
F
IGURE
4A. ICS84025 S
CHEMATIC
E
XAMPLE
S
CHEMATIC
E
XAMPLE
Figure 4A shows a schematic example of using an ICS84025. In
this example, the input is a 25MHz parallel resonant crystal with
load capacitor CL=18pF. The frequency fine tuning capacitors
C1 and C2 is 22pF and 18pF respectively. This example also
shows logic control input handling. The configuration is set at
F_SEL[1:0]=11 therefore the output frequency is 125MHz. It is
recommended to have one decouple capacitor per power pin.
Each decoupling capacitor should be located as close as pos-
sible to the power pin. The low pass filter R7, C11 and C16 for
clean analog supply should also be located as close to the V
DDA
pin as possible.
VDD
RD2
SP
R1
43
F_SEL1
RD4
SP
C7
0.1u
(U1,17)
C3
0.1u
SP = Spare, Not Installed
F_SEL1
RU3
1K
C2
18p
RD3
SP
VDD
C16
10u
VDD
C6
0.1u
VDDA
PLL_SEL
C5
0.1u
X1
25MHz,18pF
R6
43
RU4
1K
(U1,13)
F_SEL0
PLL_SEL
(U1,5)
C1
22p
Zo = 50
(U1,1)
RU2
1K
C11
0.1u
R7
10
F_SEL0
C4
0.1u
(U1,9)
Zo = 50
VDD=3.3V
U1
ICS84025
1
2
3
4
5
6
7
8
9
10
11
15
17
18
19
20
21
22
23
24
14
12
13
16
VDDO
Q0
GND
Q1
VDDO
Q2
GND
Q3
VDDO
Q4
GND
GND
VDD
VDDA
GND
XTAL2
XTAL1
MR
F_SEL1
F_SEL0
NC
Q5
VDDO
PLL_SEL
VDD
84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
9
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
F
IGURE
4B. PCB B
OARD
L
AYOUT
FOR
ICS84025
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
DDA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
21 (XTAL1) and 20 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
VDD
VIA
C1
R7
50 Ohm traces
PIN1
R3
R5
R2
R1
C7
GND
C4
C2
50 Ohm traces
C3
C16
C11
C5
R6
X1
C6
VDDA
R4
50 Ohm traces
50 Ohm traces
50 Ohm traces
50 Ohm traces
U1
84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
10
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS84025 is: 2949
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
83.2C/W
65.7C/W
57.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2C/W
39.7C/W
36.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
11
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
P
ACKAGE
O
UTLINE
- M S
UFFIX
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-013, MO-119
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
m
u
m
i
n
i
M
m
u
m
i
x
a
M
N
4
2
A
-
-
5
6
.
2
1
A
0
1
.
0
-
-
2
A
5
0
.
2
5
5
.
2
B
3
3
.
0
1
5
.
0
C
8
1
.
0
2
3
.
0
D
0
2
.
5
1
5
8
.
5
1
E
0
4
.
7
0
6
.
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e
C
I
S
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B
7
2
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0
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.
0
1
5
6
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0
1
h
5
2
.
0
5
7
.
0
L
0
4
.
0
7
2
.
1
0
8
84025EM
www.icst.com/products/hiperclocks.html
REV. A APRIL 16, 2003
12
Integrated
Circuit
Systems, Inc.
ICS84025
C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
WITH
F
ANOUT
B
UFFER
PRELIMINARY
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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