Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Functional Description
- Parallel & Serial Load Operations Diagram
- Pin Descriptions
- Pin Characteristics
- Parallel & Serial Mode Function Table
- Programmable VCO Frequency Function Table
- Programmable Output Divider Function Table
- Output Enable & Clock Enable Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Input Frequency Characteristics
- Crystal Characterisitics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- Parameter Measurement Information
- 3.3V Core/3.3V Output Load AC Test Circuit Diagram
- 3.3V Core/2.5V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- Period Jitter Diagram
- Cycle-to-Cycle Jitter Diagram
- Output Rise/Fall Time Diagram
- Output duty Cycle/Pulse Width/Period Diagram
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8402I is a general purpose, Crystal-to-
LVCMOS/LVTTL High Frequency Synthesizer and
a member of the HiPerClockS TM family of High
Performance Clock Solutions from ICS. The
ICS8402I has a selectable TEST_CLK or crystal
inputs. The VCO operates at a frequency range of 250MHz
to 700MHz. The VCO frequency is programmed in steps equal
to the value of the input reference or crystal frequency. The
VCO and output frequency can be programmed using the
serial or parallel interfaces to the configuration logic. The low
phase noise characteristics of the ICS8402I make it an ideal
clock source for Gigabit Ethernet and SONET applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
(2) LVCMOS/LVTTL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
Output frequency range: 15.625MHz - 350MHz
Crystal input frequency range: 12MHz to 40MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming counter
and output dividers
RMS period jitter: 30ps (maximum)
Cycle-to-cycle jitter: 100ps (maximum)
Full 3.3V or mixed 3.3V core/2.5V output supply voltage
-40C to 85C ambient operating temperature
Lead-Free fully RoHS compliant
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_OUT
TEST_CLK
XTAL_SEL
V
DDA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N0
N1
nc
GND
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8402I
HiPerClockSTM
ICS
OSC
OE0
OE1
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
Q0
Q1
TEST
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
PHASE DETECTOR
2
4
8
16
MR
TEST
V
DD
OE1
OE0
V
DDO
Q1
Q0
GND
XT
AL_IN
nP_LO
A
D
VCO_SEL
M0
M1
M2
M3
M4
8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
put divider to a specific default state that will automatically
occur during power-up. The TEST output is LOW when op-
erating in the parallel input mode. The relationship between
the VCO frequency, the crystal frequency and the M divider
is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 10
M 28. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by sampling
the S_DATA bits with the rising edge of S_CLOCK. The con-
tents of the shift register are loaded into the M divider and N
output divider when S_LOAD transitions from LOW-to-HIGH.
The M divide and N output divide values are latched on the
HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,
data at the S_DATA input is passed directly to the M divider
and N output divider on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and
test bits T1 and T0. The internal registers T0 and T1 deter-
mine the state of the TEST output as follows:
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the
Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8402I features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of
the LVCMOS output buffers. The divider provides a 50% out-
put duty cycle.
The programmable features of the ICS8402I support two in-
put modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Fig-
ure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on in-
puts M0 through M8 and N0 and N1 is passed directly to the
M divider and N output divider. On the LOW-to-HIGH transi-
tion of the nP_LOAD input, the data is latched and the M
divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M
and N bits can be hardwired to set the M divider and N out-
F
UNCTIONAL
D
ESCRIPTION
fVCO = fxtal x M
T1
T0
TEST Output
0
0
LOW
0
1
Shift Register Output
1
0
Output of M divider
1
1
CMOS Fout
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*NOTE: The NULL timing slot must be observed.
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
T 1
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M 0
FOUT = fVCO = fxtal x M
N
N
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
3
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
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r
8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
s
t
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IN
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8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
5
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
s
t
u
p
n
I
e
u
l
a
V
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D
N
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q
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F
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O
)
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H
M
(
1
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N
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m
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m
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UTPUT
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NABLE
& C
LOCK
E
NABLE
F
UNCTION
T
ABLE
s
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8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
6
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 3.3V5%
OR
2.5V5%, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 3.3V5%
OR
2.5V5%, T
A
= -40C
TO
85C
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M
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K
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A
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D
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V
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D
V
=
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5
6
4
.
3
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1
A
,
1
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,
0
E
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,
5
M
L
E
S
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C
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,
L
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S
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L
A
T
X
V
D
D
V
=
N
I
V
5
6
4
.
3
=
5
A
I
L
I
t
u
p
n
I
t
n
e
r
r
u
C
w
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,
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M
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1
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,
0
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,
8
M
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6
M
,
4
M
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0
M
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K
L
C
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T
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K
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A
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L
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T
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D
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S
V
D
D
,
V
5
6
4
.
3
=
V
N
I
V
0
=
5
-
A
,
1
E
O
,
0
E
O
,
5
M
L
E
S
_
O
C
V
,
L
E
S
_
L
A
T
X
V
D
D
,
V
5
6
4
.
3
=
V
N
I
V
0
=
0
5
1
-
A
V
H
O
1
E
T
O
N
;
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
V
O
D
D
V
5
6
4
.
3
=
6
.
2
V
V
O
D
D
V
5
2
6
.
2
=
8
.
1
V
V
L
O
1
E
T
O
N
;
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
5
.
0
V
NOTE 1: Outputs terminated with 50
to V
DDO
/2.
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
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i
M
l
a
c
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p
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T
m
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m
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M
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V
D
D
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a
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V
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p
p
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S
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r
o
C
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
A
D
D
e
g
a
t
l
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V
y
l
p
p
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S
g
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l
a
n
A
5
3
1
.
3
3
.
3
5
6
4
.
3
V
V
O
D
D
e
g
a
t
l
o
V
y
l
p
p
u
S
t
u
p
t
u
O
5
3
1
.
3
3
.
3
5
6
4
.
3
V
5
7
3
.
2
5
.
2
5
2
6
.
2
V
I
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
r
e
w
o
P
5
2
1
A
m
I
A
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
g
o
l
a
n
A
8
1
A
m
I
O
D
D
t
n
e
r
r
u
C
y
l
p
p
u
S
t
u
p
t
u
O
0
1
A
m
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
7
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
l
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T
O
N
T
ABLE
7A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
8
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
l
o
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T
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N
T
ABLE
7B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
9
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
O
UTPUT
R
ISE
/F
ALL
T
IME
C
YCLE
-
TO
-C
YCLE
J
ITTER
P
ERIOD
J
ITTER
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
Q0, Q1
V
DDO
2
V
DDO
2
V
DDO
2
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
Q0, Q1
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
SCOPE
Qx
LVCMOS
2.05V5%
-1.25V5%
V
DD
,
V
DDA
V
DDO
1.25V5%
V
DD
,
V
DDA
,
V
DDO
GND
GND
8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
10
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8402I provides sepa-
r a t e p owe r s u p p l i e s t o i s o l a t e a ny h i g h sw i t c h i n g
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
pin.
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
ICS8402I
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS8402I has been characterized with 18pF parallel
resonant cr ystals. The capacitor values, C1 and C2,
shown in
Figure 3 below were determined using a 25MHz,
18pF parallel resonant crystal and were chosen to mini-
mize the ppm error. The optimum C1 and C2 values can
be slightly adjusted for different board layouts.
8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
11
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8402I is: 3784
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
12
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
N
O
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A
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S
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O
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S
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I
D
L
L
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8402AYI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
13
Integrated
Circuit
Systems, Inc.
ICS8402I
350MH
Z
, C
RYSTAL
-
TO
-LVCMOS / LVTTL
F
REQUENCY
S
YNTHESIZER
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support
devices or critical medical instruments.
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