Document Outline
- General Description
- Features
- Common Configuration Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 2.5V DC Characteristics
- LVCMOS DC Characteristics
- HSTL 3.3V DC Characteristics
- HSTL 2.5V DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Parameter Measurement Information
- HSTL 3.3V Output Load AC Test Circuit Diagram
- HSTL 2.5V Output Load AC Test Circuit Diagram
- RMS Phase Jitter Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
842023AGI
www.icst.com/products/hiperclocks.html
REV. B JUNE 14, 2005
1
Integrated
Circuit
Systems, Inc.
ICS842023I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
T h e I C S 8 4 2 0 2 3 I i s a n E t h e r n e t C l o c k
Generator and a member of the HiPerClocks
TM
family of high performance devices from ICS.
For Ethernet applications, a 25MHz crystal is
used to generate 250MHz. The ICS842023I
uses ICS' 3rd generation low phase noise VCO tech-
nology and can achieve <1ps r ms phase jitter, easily
meeting Ether net jitter requirements. The ICS842023I
is packaged in a small 8-pin TSSOP, making it ideal
for use in systems with limited board space.
F
EATURES
(1) Differential HSTL output
Crystal oscillator interface, 18pF parallel resonant crystal
(24.5MHz - 34MHz)
Output frequency range: 245MHz - 340MHz
VCO range: 490MHz - 680MHz
RMS phase jitter @ 250MHz, using a 25MHz crystal
(1.875Hz - 20MHz): 0.33ps (typical)
3.3V or 2.5V operating supply
-40C to 85C ambient operating temperature
HiPerClockSTM
ICS
ICS842023I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
V
DD
Q0
nQ0
OE
8
7
6
5
B
LOCK
D
IAGRAM
OSC
Phase
Detector
VCO
490MHz - 680MHz
M = 20
(fixed)
N = 2
(fixed)
XTAL_IN
XTAL_OUT
Q0
nQ0
C
OMMON
C
ONFIGURATION
T
ABLE
- 1 Gb E
THERNET
P
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SSIGNMENT
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2
0
1
0
5
2
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
842023AGI
www.icst.com/products/hiperclocks.html
REV. B JUNE 14, 2005
2
Integrated
Circuit
Systems, Inc.
ICS842023I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
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842023AGI
www.icst.com/products/hiperclocks.html
REV. B JUNE 14, 2005
3
Integrated
Circuit
Systems, Inc.
ICS842023I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
PRELIMINARY
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
101.7C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= -40C
TO
85C
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842023AGI
www.icst.com/products/hiperclocks.html
REV. B JUNE 14, 2005
4
Integrated
Circuit
Systems, Inc.
ICS842023I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
4. C
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C
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842023AGI
www.icst.com/products/hiperclocks.html
REV. B JUNE 14, 2005
5
Integrated
Circuit
Systems, Inc.
ICS842023I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
R
ISE
/F
ALL
T
IME
HSTL 3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
HSTL 2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
RMS P
HASE
J
ITTER
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Q0
nQ0
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
SCOPE
HSTL
Qx
nQx
V
DD,
V
DDA
0V
3.3V 5%
GND
SCOPE
HSTL
Qx
nQx
0V
2.5V 5%
GND
V
DD,
V
DDA
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
842023AGI
www.icst.com/products/hiperclocks.html
REV. B JUNE 14, 2005
6
Integrated
Circuit
Systems, Inc.
ICS842023I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
PRELIMINARY
A
PPLICATION
I
NFORMATION
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS842023I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for dif-
ferent board layouts.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS842023I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
and V
DDA
should
b e i n d i v i d u a l l y c o n n e c t e d t o t h e p o w e r s u p p l y
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
pin.
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V or 2.5V
.01
F
V
DD
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
ICS842023I
842023AGI
www.icst.com/products/hiperclocks.html
REV. B JUNE 14, 2005
7
Integrated
Circuit
Systems, Inc.
ICS842023I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS842023I is: 2538
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7C/W
90.5C/W
89.8C/W
842023AGI
www.icst.com/products/hiperclocks.html
REV. B JUNE 14, 2005
8
Integrated
Circuit
Systems, Inc.
ICS842023I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
PRELIMINARY
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
8 L
EAD
TSSOP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
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Y
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i
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N
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-
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.
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1
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0
842023AGI
www.icst.com/products/hiperclocks.html
REV. B JUNE 14, 2005
9
Integrated
Circuit
Systems, Inc.
ICS842023I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
PRELIMINARY
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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