Document Outline
- General Description
- Features
- Frequency Select Function Table
- Pin Assignment
- Block Diagram
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 2.5V DC Characteristics
- LVCMOS DC Characteristics
- HSTL 3.3V DC Characteristics
- HSTL 2.5V DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise Plots
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Recommendations for Unused Input and Output Pins
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVHSTL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
1
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8421002I is a 2 output HSTL Synthesizer
optimized to generate Fibre Channel reference
clock frequencies and is a member of the
HiPerClocks
TM
family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and
53.125MHz. The ICS8421002I uses ICS' 3
rd
generation low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS8421002I is packaged in a small 20-pin
TSSOP package.
F
EATURES
Two HSTL outputs (VOHmax = 1.5V)
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz, 53.125MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.59ps (typical)
Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
-40C to 85C ambient operating temperature
Available in both standard an lead-free RoHS compliant
packages
HiPerClockSTM
ICS
1
1
0
1
0
Phase
Detector
VCO
M = 24 (fixed)
F_SEL[1:0]
0 0 3
(default)
0 1 4
1 0 6
1 1 12
2
OSC
B
LOCK
D
IAGRAM
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F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
F_SEL[1:0]
nPLL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
nXTAL_SEL
MR
Q0
nQ0
Q1
nQ1
Pulldown
Pulldown
26.5625MHz
Pulldown
Pulldown
Pulldown
ICS8421002I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
nc
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
1
2
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17
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11
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DDO
Q1
nQ1
GND
V
DD
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
P
IN
A
SSIGNMENT
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
2
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
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IN
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8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
3
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%
OR
2.5V5%, V
DDO
= 1.8V0.2V,
T
A
= -40C
TO
85C
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
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A
8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
4
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
T
ABLE
4. C
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C
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DD
= V
DDA
= 3.3V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
TO
85C
T
ABLE
3E. HSTL DC C
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V
DD
= V
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= 2.5V5%, V
DDO
= 1.8V0.2V, T
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= -40C
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8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
5
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
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= 3.3V5%, V
DDO
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A
= -40C
TO
85C
T
ABLE
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DD
= V
DDA
= 2.5V5%, V
DDO
= 1.8V0.2V, T
A
= -40C
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8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
6
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
212.5MH
Z
@ 3.3V
212.5MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.59ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
dBc
Hz
N
OISE
P
O
WER
Fibre Channel Jitter Filter
Raw Phase Noise Data
Phase Noise Result by adding
Fibre Channel Filter to raw data
T
YPICAL
P
HASE
N
OISE
AT
53.125MH
Z
@ 3.3V
53.125MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.66ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
dBc
Hz
N
OISE
P
O
WER
Fibre Channel Jitter Filter
Raw Phase Noise Data
Phase Noise Result by adding
Fibre Channel Filter to raw data
8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
7
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0, Q1
O
UTPUT
S
KEW
HSTL 2.5V/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
HSTL 3.3V/1.8V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
nQ0, nQ1
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
SCOPE
HSTL
Qx
nQx
V
DD
V
DDA
V
DDO
GND
0V
SCOPE
HSTL
Qx
nQx
V
DD
V
DDA
V
DDO
GND
0V
t
sk(o)
Qy
Qx
nQy
nQx
RMS P
HASE
J
ITTER
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
8
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS8421002I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
ICS8421002I
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8421002I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V or 2.5V
.01
F
V
DD
C1
22p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
REF_CLK I
NPUT
:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the REF_CLK to
ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
HSTL O
UTPUT
All unused HSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
9
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8421002I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8421002I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 3.465V * 122mA = 422.7mW
Power (outputs)
MAX
= 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 32.8mW = 65.6mW
Total Power
_MAX
(3.465V, with all outputs switching) = 422.7mW + 65.6mW = 488.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.488W * 66.6C/W = 117.5C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
20-
PIN
TSSOP, F
ORCED
C
ONVECTION
8421002AGI
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REV. A FEBRUARY 7, 2006
10
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in
Figure 3.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R
L
) * (V
DD_MAX
- V
OH_MAX
)
Pd_L = (V
OL_MAX
/R
L
) * (V
DD_MAX
- V
OL_MAX
)
Pd_H = (1V/50
) * (2V - 1V) = 20mW
Pd_L = (0.4V/50
) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
F
IGURE
3. HSTL D
RIVER
C
IRCUIT
AND
T
ERMINATION
V
DDO
V
OUT
RL
50
Q1
8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
11
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8421002I is: 2951
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
12
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
N
I
M
X
A
M
N
0
2
A
-
-
0
2
.
1
1
A
5
0
.
0
5
1
.
0
2
A
0
8
.
0
5
0
.
1
b
9
1
.
0
0
3
.
0
c
9
0
.
0
0
2
.
0
D
0
4
.
6
0
6
.
6
E
C
I
S
A
B
0
4
.
6
1
E
0
3
.
4
0
5
.
4
e
C
I
S
A
B
5
6
.
0
L
5
4
.
0
5
7
.
0
0
8
a
a
a
-
-
0
1
.
0
Reference Document: JEDEC Publication 95, MO-153
8421002AGI
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 7, 2006
13
Integrated
Circuit
Systems, Inc.
ICS8421002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
HSTL F
REQUENCY
S
YNTHESIZER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and F
EMTO
C
LOCKS
are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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