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843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS843001-21 is a a highly versatile, low
phase noise LVPECL Synthesizer which can
generate low jitter reference clocks for a variety
of communications applications and is a
member of the HiPerClocks
TM
family of high
performance clock solutions from ICS. The dual
crystal interface allows the synthesizer to support up to
two communications standards in a given application (i.e.
1GB Ethernet with a 25MHz crystal and 1Gb Fibre Channel
using a 25.5625MHz cr ystal). The r ms phase jitter
performance is typically less than 1ps, thus making the
device acceptable for use in demanding applications such
as OC48 SONET and 10Gb Ethernet. The ICS843001-21
is packaged in a small 24-pin TSSOP package.
F
EATURES
One 3.3V LVPECL output pair and one LVCMOS output
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
VCO range: 560MHz - 700MHz
Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.80ps (typical)
Offset
Noise Power
100Hz ............... -60.3 dBc/Hz
1kHz ............... -88.5 dBc/Hz
10kHz ............. -111.9 dBc/Hz
100kHz ............. -113.0 dBc/Hz
Full 3.3V supply mode
0C to 70C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
11
10
01
00
00
01
10
Phase
Detector
VCO
000 18
001 22
010 24
011 25
100 32
(default)
101 40
N
000 1
001 2
010 3
011 4
(default)
100 5
101 6
110 8
111 10
M
3
3
OSC
OSC
ICS843001-21
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
V
CCO
_
CMOS
N 0
N 1
N 2
V
CCO
_
PECL
Q0
nQ0
V
EE
V
CCA
V
CC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
REF_CLK
V
EE
REF_OE
M2
M1
M0
MR
SEL1
SEL0
TEST_CLK
XTAL_IN0
XTAL_OUT0
24
23
22
21
20
19
18
17
16
15
14
13
B
LOCK
D
IAGRAM
N2:N0
SEL0
SEL1
XTAL_IN0
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
TEST_CLK
MR
M2:M0
OE_REF
Q0
nQ0
Pulldown
Pulldown
Pulldown
Pulldown
REF_CLK
Pulldown
843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
2
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
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843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
3
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. C
OMMON
C
ONFIGURATIONS
T
ABLE
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843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = 0C
TO
70C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = 0C
TO
70C
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3
.
3
"
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
(LVPECL)
Continuous Current
50mA
Surge Current
100mA
Outputs, V
O
(LVCMOS)
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
70C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
5
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = 0C
TO
70C
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
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ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = 0C
TO
70C
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N
843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
622.08MH
Z
622.08MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.80ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
dBc
Hz
N
OISE
P
OWER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
Phase Noise Result by adding
Sonet OC-12 Filter to raw data
Raw Phase Noise Data
OC-12 Filter
843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
7
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
t
PD
V
CC
2
V
CCO_LVCMOS
2
P
ARAMETER
M
EASUREMENT
I
NFORMATION
REF_CLK
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0
TEST_CLK
RMS P
HASE
J
ITTER
O
UTPUT
R
ISE
/F
ALL
T
IME
3.3V LVPECL O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V0.165V
P
ROPAGATION
D
ELAY
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
V
CC
,
V
CCA
,
V
CCO_LVPECL
V
EE
nQ0
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
3.3V LVCMOS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.655%
-1.65V5%
V
CC
,
V
CCA
,
V
CCO_LVCMOS
V
EE
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
V
CCO_LVCMOS
2
t
PW
REF_CLK
843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
8
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843001-21 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 19.44MHz, 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error.
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
ICS843001-21
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843001-21 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO_x
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
. The 10
resis-
tor can also be replaced by a ferrite bead.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
9
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
outputs are designed to drive 50
transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion.
Figures 3A and 3B
show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
TEST_CLK I
NPUT
:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the TEST_CLK to
ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
10
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843001-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843001-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 170mA = 589.05mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 589.05mW + 30mW = 619.05mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.619W * 65C/W = 110.2C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
7. T
HERMAL
R
ESISTANCE


JA
FOR
24-
PIN
TSSOP, F
ORCED
C
ONVECTION


JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 4.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
4. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
12
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843001-21 is: 4057
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP


JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
13
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
24 L
EAD
TSSOP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
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843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
14
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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843001AG-21
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 26, 2005
15
Integrated
Circuit
Systems, Inc.
ICS843001-21
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
T
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