Document Outline
- General Description
- Features
- Frequency Select Function Table
- Pin Assignment
- Block Diagram
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- AC Characteristics
- Typical Phase Noise at 62.5MHz
- Typical Phase Noise at 125MHz
- Typical Phase Noise at 156.25MHz
- Parameter Measurement Information
- 3.3V Core/3.3V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- RMS Phase Jitter Diagram
- Propagation Delay Diagram
- Output Duty Cycle Pulse Width/Period Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Power Supply Filtering Techniques
- Terminatin for 3.3V LVPECL Output
- Crystal Input Interface
- Layout Guideline
- Schematic Example
- PC Board Layout Example
- Footprint Table
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Untitled
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS843002-01 is a 2 output LVPECL
synthesizer optimized to generate Ethernet
reference clock frequencies and is a member of
the HiPerClocks
TM
family of high performance
clock solutions from ICS. Using a 25MHz 18pF
parallel resonant crystal, the following frequencies can be
g e n e r a t e d b a s e d o n t h e 2 f r e q u e n c y s e l e c t p i n s
(F_SEL[1:0]): 156.25MHz, 125MHz, and 62.5MHz. The
ICS843002-01 uses ICS' 3
rd
generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase
jitter, easily meeting Ether net jitter requirements. The
ICS843002-01 is packaged in a small 20-pin TSSOP package.
F
EATURES
Two 3.3V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS single-ended input
Supports the following input frequencies:
156.25MHz, 125MHz and 62.5MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz-20MHz): 0.54ps (typical)
Typical phase noise at 156.25MHz
Phase noise:
Offset
Noise Power
100Hz ............... -97.3 dBc/Hz
1KHz .............. -119.1 dBc/Hz
10KHz .............. -126.4 dBc/Hz
100KHz .............. -127.6 dBc/Hz
Full 3.3V supply mode
Lead-Free package fully RoHS compliant
-30C to 85C ambient operating temperature
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
1
1
0
1
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
M = 25 (fixed)
F_SEL[1:0]
0 0 4
0 1 5
1 0 10
1 1
not used
OSC
2
ICS843002-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
B
LOCK
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XTAL_OUT
F_SEL1
Pulldown
Pulldown
Pulldown
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
2
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
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843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
3
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
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= V
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= V
CCO
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TO
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A
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V10%, TA = -30C
TO
85C
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-
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V10%, TA = -30C
TO
85C
l
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b
m
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HARACTERISTICS
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T
O
N
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
5
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
O
FFSET
F
REQUENCY
(H
Z
)
dBc
Hz
N
OISE
P
O
WER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
125MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.60ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
dBc
Hz
N
OISE
P
O
WER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
62.5MH
Z
62.5MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.79ps (typical)
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
Raw Phase Noise Data
10 Gigabit Ethernet Filter
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
Raw Phase Noise Data
10 Gigabit Ethernet Filter
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
156.25MH
Z
O
FFSET
F
REQUENCY
(H
Z
)
dBc
Hz
N
OISE
P
O
WER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
Raw Phase Noise Data
10 Gigabit Ethernet Filter
156.25MHz
RMS Phase Noise Jitter
1.875MHz to 20MHz = 0.54ps (typical)
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
7
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0,Q1
RMS P
HASE
J
ITTER
O
UTPUT
S
KEW
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.33V
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ARAMETER
M
EASUREMENT
I
NFORMATION
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
V
CC
,
V
CCA
, V
CCO
V
EE
nQ0, nQ1
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
sk(o)
Qy
Qx
nQy
nQx
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
8
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843002-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion.
Figures 2A and
2B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
9
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843002-01 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values shown in
Figure 3
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 25MHz 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error.
ICS843002-01
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
10
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
L
AYOUT
G
UIDELINE
Figure 4A shows a schematic example of the ICS843002-01.
An example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18 pF
F
IGURE
4A. ICS843002-01 S
CHEMATIC
E
XAMPLE
parallel resonant 26.5625MHz crystal is used. The C1=27pF
and C2=33pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy.
PC B
OARD
L
AYOUT
E
XAMPLE
Figure 4B shows an example of ICS843002-01 P.C. board lay-
out. The crystal X1 footprint shown in this example allows in-
stallation of either surface mount HC49S or through-hole HC49
package. The footprints of other components in this example
are listed in the
Table 6. There should be at least one decoupling
capacitor per power pin. The decoupling capacitors should be
located as close as possible to the power pins. The layout as-
sumes that the board has clean analog power ground plane.
F
IGURE
4B. ICS843002-01 PC B
OARD
L
AYOUT
E
XAMPLE
C1
27pF
VCC
VCCO
Zo = 50 Ohm
R6
50
C6
0.1u
C4
0.01u
VC
C
X1
25 MHz
VCC=3.3V
18pF
To Logic
Input
pins
C7
0.1u
Zo = 50 Ohm
RU1
1K
To Logic
Input
pins
C9
0.1u
Set Logic
Input to
'1'
VCCO=3.3V
VCC
VCC
R5
50
U1
ICS843002-01
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
VC
C
O
Q0
nQ
0
MR
nP
LL_S
E
L
nc
V
CCA
F
_
SEL
0
VC
C
F
_
SEL
1
X
T
A
L_O
U
T
X
T
A
L_I
N
T
E
S
T
_C
LK
nX
T
A
L_S
E
L
VC
C
VE
E
nQ
1
Q1
VC
C
O
n
c
VCC
VCCO
RD2
1K
VCCA
R4
50
C3
10uF
Zo = 50 Ohm
RD1
Not Install
R2
10
Set Logic
Input to
'0'
Zo = 50 Ohm
+
-
C8
0.1u
R7
50
Logic Control Input Examples
R9
50
C2
33pF
R8
50
+
-
RU2
Not Install
e
c
n
e
r
e
f
e
R
e
z
i
S
2
C
,
1
C
2
0
4
0
3
C
5
0
8
0
8
C
,
7
C
,
6
C
,
5
C
,
4
C
3
0
6
0
2
R
3
0
6
0
s
e
z
i
s
t
n
e
n
o
p
m
o
c
s
t
s
il
,
6
e
l
b
a
T
:
E
T
O
N
.
e
l
p
m
a
x
e
t
u
o
y
a
l
s
i
h
t
n
i
n
w
o
h
s
T
ABLE
6. F
OOTPRINT
T
ABLE
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.63V * 135mA = 490mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
_MAX
(3.63V, with all outputs switching) = 490mW + 60mW = 550mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.550W * 66.6C/W = 121.6C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7. T
HERMAL
R
ESISTANCE
JA
FOR
20-
PIN
TSSOP, F
ORCED
C
ONVECTION
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
12
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
5. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
13
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843002-01 is: 2955
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
14
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
15
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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843002AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
16
Integrated
Circuit
Systems, Inc.
ICS843002-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
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