Document Outline
- General Description
- Features
- Frequency Select Function Table
- Pin Assignment
- Block Diagram
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 2.5V DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise at 212.5MHz
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Recommendations for Unused Input and Output Pins
- Crystal Input Interface
- Termination for 3.3V LVPECL Output
- Termination for 2.5V LVPECL Output
- Layout Guideline
- Schematic Example
- PC BOard Layout Example
- Footprint Table
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
843002AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 4, 2006
1
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS843002I is a 2 output LVPECL synthesizer
optimized to generate Fibre Channel reference
clock frequencies and is a member of the
HiPerClocks
TM
family of high performance clock
solutions from ICS. Using a 26.5625MHz, 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz, and
53.125MHz. The ICS843002I uses ICS' FemtoClock
TM
low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS843002I is packaged in a small 20-pin
TSSOP package.
F
EATURES
Two 3.3V or 2.5V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @212.5MHz (2.55MHz - 20MHz):
0.50ps (typical)
Full 3.3V or 2.5V supply modes
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
1
1
0
1
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
OSC
M = 24 (fixed)
F_SEL[1:0]
0 0 3
0 1 4
1 0 6
1 1 12
2
ICS843002I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
B
LOCK
D
IAGRAM
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
F_SEL[1:0]
nPLL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
nXTAL_SEL
MR
Q0
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Q1
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Pulldown
26.5625MHz
nc
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CCO
Q0
nQ0
MR
nPLL_SEL
nc
V
CCA
F_SEL0
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CCO
Q1
nQ1
V
EE
V
CC
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
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Pulldown
Pulldown
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1
843002AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 4, 2006
2
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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843002AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 4, 2006
3
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V10%, T
A
= -40C
TO
85C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
73.2C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 2.5V5%, T
A
= -40C
TO
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ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V10%
OR
2.5V5%, T
A
= -40C
TO
85C
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=
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.
3
=
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-
A
843002AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 4, 2006
4
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V10%, T
A
= -40C
TO
85C
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
T
ABLE
3D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V10%
OR
2.5V5%, T
A
= -40C
TO
85C
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T
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N
843002AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 4, 2006
5
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 2.5V5%, T
A
= -40C
TO
85C
l
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843002AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 4, 2006
6
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
212.5MHz
RMS Phase Jitter (Random)
2.55MHz to 20MHz = 0.50ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
dBc
Hz
Fibre Channel Jitter Filter
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
N
OISE
P
OWER
T
YPICAL
P
HASE
N
OISE
AT
212.5MH
Z
@ 3.3V
843002AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 4, 2006
7
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
Q0, Q1
t
PD
REF_CLK
RMS P
HASE
J
ITTER
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V 0.33V
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
V
CC
,
V
CCA
, V
CCO
V
EE
nQ0, nQ1
O
UTPUT
R
ISE
/F
ALL
T
IME
t
sk(o)
Qy
Qx
nQy
nQx
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0, Q1
nQ0, nQ1
P
ROPAGATION
D
ELAY
O
UTPUT
S
KEW
SCOPE
Qx
nQx
LVPECL
2V
-0.5V 0.125V
V
CC
,
V
CCA
, V
CCO
V
EE
843002AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 4, 2006
8
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843002I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
. The 10
resis-
tor can also be replaced by a ferrite bead.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V or 2.5V
.01
F
V
CC
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
REF_CLK I
NPUT
:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the REF_CLK to
ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
843002AGI
www.icst.com/products/hiperclocks.html
REV. A JANUARY 4, 2006
9
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843002I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 26.5625MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
ICS843002I
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
outputs are designed to drive 50
transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion.
Figures 3A and 3B
show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
843002AGI
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REV. A JANUARY 4, 2006
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Integrated
Circuit
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ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
T
ERMINATION
FOR
2.5V LVPECL O
UTPUT
Figure 4A
and
Figure 4B
show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to ter-
minating 50
to V
CC
- 2V. For V
CCO
= 2.5V, the V
CCO
- 2V is very
close to ground level. The R3 in Figure 4B can be eliminated
and the termination is shown in
Figure 4C.
F
IGURE
4C. 2.5V LVPECL T
ERMINATION
E
XAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driv er
F
IGURE
4B. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driv er
Zo = 50 Ohm
+
-
2.5V
F
IGURE
4A. 2.5V LVPECL D
RIVER
T
ERMINATION
E
XAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driv er
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V
843002AGI
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REV. A JANUARY 4, 2006
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Integrated
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Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
L
AYOUT
G
UIDELINE
Figure 5A
shows a schematic example of the ICS843002I. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an
F
IGURE
5A. ICS843002I S
CHEMATIC
E
XAMPLE
18pF parallel resonant 26.5625MHz crystal is used. The
C1=27pF and C2=33pF are recommended for frequency ac-
curacy. For different board layout, the C1 and C2 may be
slightly adjusted for optimizing frequency accuracy.
F
IGURE
5B. ICS843002I PC B
OARD
L
AYOUT
E
XAMPLE
PC B
OARD
L
AYOUT
E
XAMPLE
Figure 5B
shows an example of ICS843002I P.C. board layout.
The crystal X1 footprint shown in this example allows installa-
tion of either surface mount HC49S or through-hole HC49 pack-
age. The footprints of other components in this example are listed
in the
Table 6.
There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that
the board has clean analog power ground plane.
T
ABLE
6. F
OOTPRINT
T
ABLE
e
c
n
e
r
e
f
e
R
e
z
i
S
2
C
,
1
C
2
0
4
0
3
C
5
0
8
0
8
C
,
7
C
,
6
C
,
5
C
,
4
C
3
0
6
0
2
R
3
0
6
0
s
e
z
i
s
t
n
e
n
o
p
m
o
c
s
t
s
il
,
6
e
l
b
a
T
:
E
T
O
N
.
e
l
p
m
a
x
e
t
u
o
y
a
l
s
i
h
t
n
i
n
w
o
h
s
ICS843002I
C7
0.1u
C1
27pF
Zo = 50 Ohm
C4
0.01u
C9
0.1u
To Logic
Input
pins
VCC
U1
ICS843002i
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
V
CCO
Q0
nQ
0
MR
nP
L
L_S
E
L
nc
VC
C
A
F
_
SEL
0
VC
C
F
_
SEL
1
XT
AL
_
O
U
T
XT
AL
_
I
N
RE
F
_
CL
K
nX
T
A
L_S
E
L
VC
C
VE
E
nQ
1
Q1
VC
C
O
n
c
R9
50
Logic Control Input Examples
VCC
Set Logic
Input to
'0'
R3
133
Set Logic
Input to
'1'
R8
50
Zo = 50 Ohm
RU2
Not Install
Zo = 50 Ohm
R2
10
C6
0.1u
R4
82.5
R7
50
R5
133
C3
10uF
VCCO=3.3V
+
-
Optional Termination
RD1
Not Install
VCC
VCCO
VCC=3.3V
+
-
VC
C
VCCA
3.3V
RD2
1K
To Logic
Input
pins
VCCO
C2
33pF
C8
0.1u
RU1
1K
Zo = 50 Ohm
VCC
18pF
X1
26.5625MHz
R6
82.5
843002AGI
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REV. A JANUARY 4, 2006
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Integrated
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Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 10% = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.63V * 130mA = 471.9mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
_MAX
(3.63V, with all outputs switching) = 471.9mW + 60mW = 531.9mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.532W * 66.6C/W = 120.4C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
ABLE
7. T
HERMAL
R
ESISTANCE
JA
FOR
20-
PIN
TSSOP, F
ORCED
C
ONVECTION
843002AGI
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REV. A JANUARY 4, 2006
13
Integrated
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Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
6. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
843002AGI
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REV. A JANUARY 4, 2006
14
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843002I is: 2578
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
20 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843002AGI
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REV. A JANUARY 4, 2006
15
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
20 L
EAD
TSSOP
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
N
I
M
X
A
M
N
0
2
A
-
-
0
2
.
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843002AGI
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REV. A JANUARY 4, 2006
16
Integrated
Circuit
Systems, Inc.
ICS843002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-3.3V, 2.5V
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and F
EMTO
C
LOCKS
are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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