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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
T h e I C S 8 4 3 0 0 2 - 3 1 i s a m e m b e r o f t h e
HiperClockSTM family of high performance clock
solutions from ICS. This monolithic device is a
high-performance, PLL-based synchronous
clock generator and jitter attenuation circuit. The
ICS843002-31 contains two clock multiplication stages that
are cascaded in series. The first stage is a VCXO-based PLL
that is optimized to provide reference clock jitter attenuation,
to be jitter tolerant, and to provide a stable reference clock
for the second multiplication stage. The second stage is the
proprietary ICS FemtoClockTM
circuit which is a high-frequency,
sub-picosecond clock multiplier.
The VCXO PLL has an on-chip VCXO circuit that uses an
external, inexpensive pullable crystal in the 17.5 to 25MHz
range. The PLL includes 13 bit reference and feedback
dividers supporting complex PLL multiplication ratios and
input reference clock rates as low as 2.3kHz. External loop
filter components are used (two resistors and two capacitors)
to achieve the low loop bandwidth needed for jitter atten-
uation of a recovered data clock.
The FemtoClock circuit can multiply the VCXO crystal
frequency by a factor of 28 or 32 (selectable) and provide a
clock output of up to 700MHz.
Clock Input/Output Configuration:
Clock Inputs - one differential pair, two singled ended
(mux selected)
Differential input pair can support LVPECL, LVDS,
LVHSTL, SSTL, HCSL or single-ended LVCMOS
or LVTTL levels
Singled ended inputs can support LVCMOS or
LVTTL levels
Clock Outputs, FemtoClockS two LVPECL pairs
(selectable output dividers)
Clock Output, VCXO one single ended output
(at VCXO crystal frequency)
Clock Output, other VCXO reference clock
Example Applications:
SONET/SDH line card clock generator (up to 622.08MHz
for OC-48) using 8kHz frame clock as input reference
Jitter attenuation of a recovered communications clock
Complex-ratio clock frequency translation between
various communication protocols, such as:
For telecom, OC-12 to E3 rate conversion, 622.08MHz
to 34.368MHz, PLL ratio of 179/32
For digital video, ITU-R601 to SMPTE 252M/59.94,
27MHz to 74.17582MHz, PLL ratio of 250/91
P
IN
A
SSIGNMENT
F
EATURES
Outputs:
Two high frequency differential LVPECL outputs
Output frequency: up to 700MHz
One LVCMOS/LVTTL VCXO PLL output with output
enable
One Reference clock output with output enable
One LOCK detect output
Input mux supports 3 selectable inputs: one differential
input pair and two LVCMOS/LVTTL input clocks
13-bit VCXO PLL feedback and reference dividers provide
wide range of frequency translation ratio options
FemtoClock frequency multiplier supports rate of:
560MHz - 700MHz
`Lock Detect' output reports lock status of VCXO PLL
VCXO PLL circuit provides jitter attenuation with
loop bandwidth of 250Hz and below (user adjustable)
RMS phase jitter, random at 12kHz to 20MHz:
<1ps (design target)
3.3V supply voltage
0C to 70C ambient operating temperature
Industrial temperature information available upon request
Available in both standard and lead-free RoHS-compliant
packages
HiPerClockSTM
ICS
64-Lead TQFP, EPAD
10mm x 10mm x 1.0mm
package body
Y package
Top View
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ICS843002-31
V
EE
REF_CLK
VCLK
LOCK
V
CCO
_
CMOS
nQB
Q B
V
EE
nQA
Q A
V
CCO
_
PECL
MP
NPB0
NPB1
NPB2
V
CCA
LF1
LF0
ISET
V
EE
NV1
NV0
V
CC
MR
CLK0
nCLK0
OE_REF
CLK1
V
CC
SEL1
SEL0
CLK2
XOIN12
XOIN11
XOIN10
XOIN9
XOIN8
XOIN7
XOIN6
XOIN5
XOIN4
XOIN3
XOIN2
XOIN1
XOIN0
NP
A2
NP
A1
NP
A0
V
CCA
_
XO
XT
AL_IN
X
T
AL_OUT
XOFB0
XOFB1
XOFB2
XOFB3
XOFB4
XOFB5
XOFB6
XOFB7
XOFB8
XOFB9
XOFB10
XOFB11
XOFB12
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
2
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
B
LOCK
D
IAGRAM
- N
OMINAL
S
YSTEM
C
ONFIGURATION
00
01
10
11
Bypass
Input Divider
XOIN[12:0]
1 to 8191
VCXO PLL
FemtoClockTM
Frequency
Multiplier
VCXO PLL
Feedback Divider
XOFB[12:0]
1 to 8191
VCXO PLL Output
Divider NV[1:0]
00: 1
01: 12
10: 16
11: Disabled Drive Low
QA Output
Divider NPA[2:0]
000: 1
001: 2
010: 4
011: 8
100: 12
101: 14
110: 16
111: Disabled
Drive Low
QB Output
Divider NPB[2:0]
000: QA 1
001: QA 2
010: QA 4
011: QA 8
100: XOIN Output
101: OFB Output
110: MP Output
111: Disabled
Drive Low
LOCK Detect
3
3
2
13
13
ISET
Charge Pump Current
17.5 - 25MHz
External Loop
Filter Connection
XT
AL_IN
XT
AL_OUT
LF0 LF1
>1 1
0: x32
1: x28
NPB[2:0]
NPA[2:0]
NV[1:0]
CLK0
nCLK0
CLK1
CLK2
SEL1
SEL0
XOIN[12:0]
XOFB[12:0]
MP
OE_REF
VCLK
Q A
nQA
Q B
nQB
REF_CLK
LOCK
NOTE 1: For application configuration (non-test/bypass modes).
NOTE 2: Bold lines are primary clock paths (non-control/non-feedback lines).
Not all control lines and signal paths are shown in this simplified block diagram.
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
3
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
S
IMPLIFIED
B
LOCK
D
IAGRAM
- C
LOCK
S
IGNAL
P
ATHS
IN
B
YPASS
M
ODE
1 1 Bypass
0 1
1 0
Input Divider
XOIN[12:0]
1 to 8191
ISET
Charge Pump
Current
17.5 - 25MHz
External Loop
Filter Connection
LF0 LF1
XT
AL_OUT
XT
AL_IN
VCXO PLL
VCXO PLL Output
Divider NV[1:0]
00: 1
01: 12
10: 16
11: Disabled Drive Low
VCXO PLL
Feedback Divider
XOFB[12:0]
1 to 8191
QA Output
Divider NPA[2:0]
NPA[2:0]
000: 1
001: 2
010: 4
011: 8
100: 12
101: 14
110: 16
111: Disabled Drive Low
FemtoClockTM
Feedback Divider
MP
0: 32
1: 28
000: 1
001: 2
010: 4
011: 8
111: Disabled
110: MP
101: XOFB
100: XOIN
FemtoClockTM
Frequency
Multiplier
VCLK
QA
nQA
QB
nQB
CLK0
nCLK0
SEL1 = 1
SEL0 = 1
CLK1
CLK2
NPB2
NPB1
NPB0
NOTE 1: Setting SEL1:SEL0 = 11 enables bypass mode.
Only clock signals on the CLK0/nCLK0 input pair are routed
to the device in bypass mode.
NOTE 2: Bold lines show clock bypass paths.
Not all control lines and signal paths are shown in this
simplified block diagram.
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
T
ABLE
1. P
IN
D
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
5
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
T
ABLE
2. P
IN
C
HARACTERISTICS
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7
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
S
ECTION
1. F
REQUENCY
T
RANSLATION
The ICS843002-31 is a two stage device, a VCXO PLL stage
followed by a low phase noise FemtoClock multiplier stage.
The VCXO uses a pullable crystal to lock to the reference
clock and can provide an output frequency up to 25MHz on
the single-ended VCLK output. For higher frequencies, the low
phase noise FemtoClock can multiply the VCXO PLL out-
put clock up to 700MHz on 2 differential LVPECL output
pairs (QA/nQA, QB/nQB).
The VCXO PLL stage has a 13-bit input divider and a 13-bit
feedback divider to generate large integer ratios needed for
some frequency translation applications. When configuring
the device is to use pullable crystals in the 17.5MHz 25MHz
range on the VCXO PLL stage, and ensure that the
FemtoClock PLL is kept within its range of 560MHz to 700MHz.
Below are 3 examples:
1. 8kHz to 622.08MHz and 155.52MHz
This frequency translation requires use of both the VCXO
PLL and the FemtoClock circuit. The VCXO PLL can be used
to multiply up to 19.44MHz for use as a reference clock for
the FemtoClock which will do the multiplication from
19.44MHz to 622.08MHz.
Using a 19.44MHz pullable crystal on XTAL_IN/
XTAL_OUT, set the VCXO PLL feedback divider pins,
XOFB[12:0], to 2430. This multiplies the 8kHz refer-
ence clock to 19.44MHz.
Set the FemtoClock multiplication control pin, MP, to
0 which sets the multiplication factor to 32. This sets
the FemtoClock VCO to 622.08MHz.
Set the QA/nQA output divider control pins,
NPA[2:0] = 000 for divide by 1. This sets the QA/nQA
LVPECL output pair for 622.08MHz.
Set the QB/nQB output divider control pins,
NPB[2:0] = 010 for divide by 4. This sets the QB/nQB
LVPECL output pair for 155.52MHz.
2. T1 to T3. (1.544MHz to two 44.736MHz outputs)
Since 44.736MHz is slightly higher than the maximum VCXO
output frequency, the FemtoClock circuit will have to be used.
Using a pullable 22.368MHz on XTAL_IN/XTAL_OUT,
set the VCXO PLL feedback divider pins, XOFB[12:0]
to 2796 and the input divider pins, XOIN[12:0] to 193.
This multiplies the 1.544MHz reference to 22.368MHz
(1.544MHz * 2796/193 = 22.368MHz).
Set the FemtoClock multiplication control pin, MP, to
28 which sets the VCO at 626.304MHz.
Set the QA/nQA output divider control pins,
NPA[2:0] = 101 for divide by 14. This sets the QA/nQA
LVPECL output pair for 44.736MHz.
Set the QB/nQB output divider control pins,
NPB[2:0] = 000 for divide by 1. This sets the QB/nQB
LVPECL output pair for 44.736MHz
3. T1 to E1. (1.544MHz to two 2.048MHz outputs)
The 2.048MHz output frequency requirement is low enough
that the FemtoClock circuit is not required. Only the VCXO
stage is used for this frequency translation.
Using a pullable 24.576MHz on XTAL_IN/XTAL_OUT,
set the VCXO PLL feedback divider pins, XOFB[12:0]
to 3072 and the input divider pins, XOIN[12:0] to 193.
This multiplies the 1.544MHz reference to 2.048MHz
(1.544MHz * 3072/193 = 24.576MHz).
Set the VCXO PLL Output Divider control pins,
NV[1:0] = 01 for /12. This divides the 24.576MHz VCXO
PLL frequency down to 2.048MHz.
The Frequency Configuration Table Examples (see the follow-
ing pages) are intended to show the most common frequency
translation requirements. It is sorted in order of descending
input frequency. It is not intended to be an exhaustive configur-
ation table because that would be impractical with almost 3
billion possible configurations. As far as configuration is
concerned, frequencies <= 25MHz can be generated with the
VCXO PLL while frequencies > 25MHz require the use of the
downstream FemtoClock which can multiply the VCXO PLL
output up to 700MHz. Complex integer ratios are handled with
the VCXO PLL stage and the FemtoClock circuit can be
configured to multiply the VCXO PLL output by 32 or 28. The
following example will illustrate the configuration process.
Assume you have a 1.544MHz T1 clock which needs to be
multiplied up to 622.08MHz (OC12). Obviously, the
FemtoClock multiplier will be needed to achieve 622.08MHz.
Since the FemtoClock has a selectable multiplication factor
of 28 or 32, this means there are 2 viable VCXO PLL crystal
choices which fall within its 17.5MHz 15MHz range:
22.217143MHz (/28 feedback divider) or 19.44MHz (/32
feedback divider). Use of the /28 feedback divider for the
FemtoClock multiplier will give slightly better phase noise,
but in this case 22.217143/1.544 cannot be exactly
achieved with the 13-bit input and feedback VCXO PLL
dividers. Using the x32 setting of the FemtoClock allows a
ratio of 19.44/1.544 = 2430/193 which is easily achievable.
So the FemtoClock would be set for x32 and a 19.44MHz
crystal would be used. The VCXO PLL input divider would
be set for 193 and the VCXO PLL feedback divider would
be set for 2430. To double check the solution, perform the
following calculation: 1.544 * 2430 * 32/193 = 622.08MHz.
The 2
nd
FemtoClock multiplier output, QB/nQB, can be set to
equal the QA/nQA output frequency or a fraction of its frequency.
The following fractional values are available: /1, /2, /4, /8.
S
ECTION
2. F
REQUENCY
C
ONFIGURATION
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
7
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
T
ABLE
3A.
F
REQUENCY
C
ONFIGURA
TION
E
XAMPLES
,
CONTINUED
ON
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
8
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
9
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
10
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
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PRELIMINARY
T
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3A.
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
T
ABLE
3A.
F
REQ
UENCY
C
ONFIGURA
TION
E
XAMPLES
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
12
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCA_XO
= V
CCO_CMOS
= V
CCO_PECL
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCA_XO
= V
CCO_CMOS
= 3.3V5%, T
A
= 0C
TO
70C
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0
V
NOTE 1: Outputs terminated with 50
to V
CCO_CMOS
/2.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, V
O
(LVCMOS)
-0.5V to V
CCO
+ 0.5V
Outputs, I
O
(LVPECL)
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
22.3C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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5
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m
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
13
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCA_XO
= V
CCO_PECL
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCA_XO
= V
CCO_CMOS
= V
CCO_PECL
= 3.3V5%, T
A
= 0C
TO
70C
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
14
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCA_XO
= V
CCO_CMOS
= V
CCO_PECL
= 3.3V5%, T
A
= 0C
TO
70C
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
15
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
LVPECL O
UTPUT
S
KEW
3.3V LVCMOS O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V LVPECL O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
LVCMOS O
UTPUT
S
KEW
LVPECL O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/tP
ERIOD
-1.3V 0.165V
t
sk(o)
nQA
QA
nQB
QB
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
QA, QB
nQA, nQB
V
EE
V
CC
,
V
CCA
,
V
CCA_XO,
V
CCO_PECL
LVCMOS O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/tP
ERIOD
t
sk(o)
V
DDO
2
V
DDO
2
VCLK
REF_CLK
SCOPE
Qx
LVCMOS
1.65V 5%
-1.65V 5%
V
EE
V
CC
,
V
CCA
,
V
CCA_XO,
V
CCO_CMOS
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
V
CCO_LVCMOS
2
t
PW
VCLK,
REF_CLK
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
16
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
LVCMOS O
UTPUT
R
ISE
/F
ALL
T
IME
LVPECL O
UTPUT
R
ISE
/F
ALL
T
IME
P
HASE
J
ITTER
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
17
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
The above equation calculates the "normalized" loop bandwidth
(denoted as "NBW") which is approximately equal to the - 3dB
bandwidth. NBW does not take into account the effects of
damping factor or the second pole imposed by C
P
. It does,
however, provide a useful approximation of filter performance.
To prevent jitter on VCLK due to modulation of the VCXO PLL
by the phase detector frequency, the following general rule
should be observed:
(Phase Detector) = Input Frequency XOIN
The PLL loop damping factor (DF) is determined by:
W
HERE
:
C
S
= Value of capacitor C
S
in loop filter in farads
D
ESCRIPTION
OF
THE
PLL S
TAGES
The ICS843002-31 is a two stage frequency multiplication
device, a VCXO PLL followed by a low phase noise
FemtoClock frequency multiplier. The VCXO uses an external
pullable crystal which can be pulled 100ppm by the VCXO
PLL circuitry to phase lock it to the input reference frequency.
The output frequency of the VCXO PLL is equal to that of the
external pullable crystal, which is in the range of 17.5MHz to
25MHz. The loop bandwidth VCXO PLL is typically set in the
range of 10-250Hz which provides attenuation of input
reference clock jitter. Since the VCXO is a high-Q oscillator
circuit, it has low intrinsic output jitter and phase noise. The
VCXO PLL output clock is available from the VCLK pin.
The FemtoClock frequency multiplier has an effective
control bandwidth of about 800kHz which means it will track
the VCXO PLL clock output.
VCXO PLL L
OOP
R
ESPONSE
C
ONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected
by the setting of the VCXO feedback divider value (XOFB)
and by the external loop filter components. A practical range
of loop bandwidth for many applications is 25Hz to 1kHz.
A bandwidth of less than 10Hz requires careful component
selection and possible metal shielding to prevent clock output
wander. A damping factor of 0.7 or greater should be used
to ensure loop stability. When a passband peaking of <0.1dB
is desired for SONET/SDH loop timing application, the
damping factor should be 6 or higher.
A PC base PLL bandwidth calculator is also under develop-
ment. For assistance with loop filter bandwidth and com-
ponent selection suggestions, please contact your ICS
sales representative.
S
ETTING
THE
VCXO PLL L
OOP
R
ESPONSE
The VCXO PLL loop response is determined both by fixed
device characteristics and by other characteristics set by
the user. This includes the values of R
S
, C
S
, C
P
and R
SET
as shown in the External VCXO PLL Components figure on
this page.
The VCXO PLL loop bandwidth is approximated by:
W
HERE
:
R
S
= Value of resistor R
S
in loop filter in ohms
I
CP
= Charge pump current in amps (see table on page 17)
K
O
= VCXO Gain in Hz/V (see table on page 18)
XOFB Divider = 1 to 8191
A
PPLICATION
I
NFORMATION
NBW (VCXO PLL) =
R
S
x I
CP
x K
O
2
x XOFB Divider
NBW (VCXO PLL)
(Phase Detector)
20
DF (VCLK) = x
R
S
2
I
CP
x C
S
x K
O
XOFB Divider
1
2
3
64 63 62
LFR
LF
ISET
C
S
R
S
C
P
R
SET
optional
optional
F
IGURE
1. E
XTERNAL
VCXO PLL C
OMPONENTS
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
18
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
C
P
=
C
S
20
N
OTES
ON
SETTING
THE
VALUE
OF
C
P
As another general rule, the following relationship should be
maintained between components C
S
and C
P
in the loop filter:
C
P
establishes a second pole in the VCXO PLL loop filter.
For higher damping factors (> 1), calculate the value of C
P
based on a C
S
value that would be used for a damping
factor of 1. This will minimize baseband peaking and loop
instability that can lead to output jitter.
C
P
also dampens VCXO PLL input voltage modulation by the
charge pump correction pulses. A C
P
value that is too low will
result in increased output phase noise at the phase detector
frequency due to this. In extreme cases where input jitter is
high, charge pump current is high, and C
P
is too small, the
VCXO PLL input voltage can hit the supply or ground rail
resulting in non-linear loop response.
The best way to set the value of C
P
is to use the filter response
software available from ICS (please refer to the following
section). C
P
should be increased in value until it just starts
affecting the passband peak.
N
OTES
ON
E
XTERNAL
C
RYSTAL
L
OAD
C
APACITORS
In the loop filter schematic diagram, capacitors are shown
from pin 62 to ground and pin 63 to ground. These are
optional crystal load capacitors which can be used to cen-
ter tune the external pullable crystal (the crystal frequency
can only be lowered by adding capacitance, it cannot be
raised). Note that the addition of external load capacitors
will decrease the crystal pull range and the Kvco value.
L
OOP
F
ILTER
R
ESPONSE
S
OFTWARE
Online tools to calculate loop filter response can be found at
www.icst.com.
N
OTES
ON
S
ETTING
C
HARGE
P
UMP
C
URRENT
The recommended range for the charge pump current is
50
A to 500A. Below 50A, loop filter charge leakage,
due to PCB or capacitor leakage, can become a problem.
This loop filter leakage can cause locking problems, output
clock cycle slips, or low frequency phase noise.
As can be seen in the loop bandwidth and damping factor
equations or by using the filter response software available
from ICS, increasing charge pump current (I
CP
) increases
both bandwidth and damping factor.
R
T
E
S
I
(
t
n
e
r
r
u
C
p
m
u
P
e
g
r
a
h
C
P
C
)
K
6
.
7
1
A
5
.
2
6
K
8
.
8
A
5
2
1
K
4
.
4
A
0
5
2
K
2
.
2
A
0
0
5
1E-3
100E-6
10E-6
1k
10k
100k
R
SET
,
I
CP
, Amps
F
IGURE
2. C
HARGE
P
UMP
C
URRENT
VS
. V
ALUE
OF
R
SET
(
EXTERNAL
RESISTOR
) G
RAPH
C
HARGE
P
UMP
C
URRENT
, E
XAMPLE
S
ETTINGS
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
19
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
VCXO G
AIN
(K
O
)
VS
. XTAL F
REQUENCY
e
l
p
m
a
x
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e
s
a
C
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b
m
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t
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r
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f
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c
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n
o
i
t
c
e
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e
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t
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e
n
o
p
m
o
C
r
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t
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p
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r
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t
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p
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.
0
8
1
8
.
5
1
.
0
2
z
H
k
8
4
4
.
9
1
1
0
3
4
2
0
5
.
4
0
5
1
2
.
2
1
0
.
0
9
1
8
.
2
3
.
0
3
z
H
k
4
4
.
9
1
4
4
.
9
1
2
3
2
3
0
9
0
.
9
1
1
0
1
1
0
.
0
5
6
7
.
2
3
.
0
4
z
H
M
4
4
.
9
1
4
4
.
9
1
8
8
0
9
0
.
9
1
1
0
1
1
0
.
0
0
8
1
3
.
5
1
.
0
E
XAMPLE
L
OOP
F
ILTER
C
OMPONENT
V
ALUE
8000
7000
6000
5000
4000
16
18
20
22
24
26
9000
XTAL Frequency (MHz)
K
VCO
(Hz/V)
843002CY-31
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REV. B NOVEMBER 22, 2005
20
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843002-31 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, V
CCA_XO
,
and V
CCO_X
should be individually connected to the power sup-
ply plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 3
illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
3. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
F
IGURE
4C. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
4B. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
4D. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK0 /nCLK0 accepts LVDS, LVPECL, LVHSTL, SSTL,
HCSL and other differential signals. Both V
SWING
and V
OH
must
meet the V
PP
and V
CMR
input requirements.
Figures 4A to 4D
show interface examples for the HiPerClockS CLK0/nCLK0
input driven by the most common driver types. The input inter-
faces suggested here are examples only. Please consult with
F
IGURE
4A. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
the vendor of the driver component to confirm the driver termi-
nation requirements. For example in
Figure 4A,
the input ter-
mination applies for ICS HiPerClockS LVHSTL drivers. If you
are using an LVHSTL driver from another vendor, use their
termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
21
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
F
IGURE
5. S
INGLE
-E
NDED
C
LOCK
I
NPUT
I
NTERFACE
3.3V
CLK
nCLK
3.3V
51k
51k
51k
(no connection)
Differential
Input Stage
LVTTL
or LVCMOS
Logic Output
Series
Termination
Optional
Series
Filter
Resistor
nCLK0
CLK0
Internal Device Circuitry
External Circuitry
D
IFFERENTIAL
C
LOCK
I
NPUT
C
IRCUIT
U
SING
THE
D
IFFERENTIAL
I
NTERFACE
FOR
S
INGLE
-E
NDED
C
LOCKS
The differential interface (CLK0/nCLK0) can be used as a
third single-ended input to support an LVCMOS or LVTTL
clock driver. The clock input is connected to the CLK0 input
pin, and the nCLK0 pin is left unconnected. To help reduce
interference with the internal VCO circuits, an external
resistor can be placed in series with the clock signal near
the CLK0 input pint. Combined with the input pin capaci-
tance, this resistor acts as a low pass signal filter. The
typical value of this optional series filter resistor is 100
.
This will lower both the amplitude and edge rate of the
clock input signal. In the case of a very short clock trace a
series termination register may not be needed.
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
resistor can be tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the CLK input to
ground.
CLK/nCLK I
NPUT
:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
resistor can be tied from
CLK to ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
22
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
7B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
7A. LVPECL O
UTPUT
T
ERMINATION
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion.
Figures 7A and
7B
show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and
clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
EXPOSED PAD
Expose Metal Pad
(GROUND PAD)
GROUND PLANE
SOLDER
SIGNAL
TRACE
SIGNAL
TRACE
THERM AL VIA
SOLDER M ASK
F
IGURE
6. P.C. B
OARD
FOR
E
XPOSED
P
AD
T
HERMAL
R
ELEASE
P
ATH
E
XAMPLE
T
HERMAL
R
ELEASE
P
ATH
The exposed metal pad provides heat transfer from the
device to the P.C. board. The exposed metal pad is ground
pad connected to ground plane through thermal via. The
exposed pad on the device to the exposed metal pad on the
PCB is contacted through solder as shown in
Figure 6.
For
further information, please refer to the Application Note on
Surface Mount Assembly of Amkor's Thermally /Electrically
Enhance Leadframe Base Package, Amkor Technology.
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
23
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843002-31.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843002-31 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 395mA = 1368.67mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
_MAX
(3.465V, with all outputs switching) = 1368.67mW + 60mW = 1428.67mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 17.2C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 1.429W * 17.2C/W = 94.6C. This is well below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).


JA
by Velocity (Linear Feet per Minute)
T
ABLE
7. T
HERMAL
R
ESISTANCE


JA
FOR
64-
PIN
TQFP, F
ORCED
C
ONVECTION
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
22.3C/W
17.2C/W
15.1C/W
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
24
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 8.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
) * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
8. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CCO
R L
50
V
CCO
- 2V
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
25
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843002-31 is: 10,095
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
64 L
EAD
TQFP, EPAD


JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
22.3C/W
17.2C/W
15.1C/W
843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
26
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
64 L
EAD
TQFP, EPAD
(32 pin package depicted to define Table 9 dimension symbols)
T
ABLE
9. P
ACKAGE
D
IMENSIONS
FOR
64 L
EAD
TQFP, EPAD
Reference Document: JEDEC Publication 95, MS-026
N
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
27
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MH
Z
F
EMTO
C
LOCKS
TM VCXO B
ASED
F
REQUENCY
T
RANSLATOR
AND
J
ITTER
A
TTENUATOR
PRELIMINARY
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
The aforementioned trademarks, HiPerClockS and F
EMTO
C
LOCKS
are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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