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Электронный компонент: ICS843004

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843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
1
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS843004 is a 4 output LVPECL synthesizer
optimized to generate Fibre Channel reference
clock frequencies and is a member of the
HiPerClocks
TM
family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25, 106.25MHz, and
53.125MHz. The ICS843004 uses ICS' 3
rd
generation low phase
noise VCO technology and can achieve 1ps or lower typical
rms phase jitter, easily meeting Fibre Channel jitter requirements.
The ICS843004 is packaged in a small 24-pin TSSOP package.
F
EATURES
Four 3.3V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25, 106.25MHz, 53.125MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637KHz - 10MHz): 0.72ps (typical)
RMS phase noise at 212.5MHz (typical)
Phase noise:
Offset
Noise Power
100Hz ............... -95.0 dBc/Hz
1KHz .............. -114.3 dBc/Hz
10KHz .............. -123.8 dBc/Hz
100KHz .............. -124.6 dBc/Hz
Full 3.3V supply mode
-30C to 85C ambient operating temperature
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
1
1
0
1
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
M = 24 (fixed)
F_SEL[1:0]
0 0 3
0 1 4
1 0 6
1 1 12
2
OSC
ICS843004
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQ1
Q1
V
CC
o
Q0
nQ0
MR
nPLL_SEL
nc
V
CCA
F_SEL0
V
CC
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
nQ2
Q2
V
CCO
Q3
nQ3
V
EE
nc
nXTAL_SEL
TEST_CLK
V
EE
XTAL_IN
XTAL_OUT
24
23
22
21
20
19
18
17
16
15
14
13
B
LOCK
D
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Q2
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Q3
nQ3
Pulldown
Pulldown
26.5625MHz
Pulldown
Pulldown
Pulldown
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
2
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
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843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
3
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = -30C
TO
85C
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = -30C
TO
85C
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A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
70C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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1
A
m
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = -30C
TO
85C
l
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C
.
V
2
-
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
4
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = -30C
TO
85C
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
r
e
t
e
m
a
r
a
P
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N
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
5
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
106.25MH
Z
106.25MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.81ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
Fibre Channel Jitter Filter
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
dBc
Hz
N
OISE
P
O
WER
T
YPICAL
P
HASE
N
OISE
AT
53.125MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
53.125MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.98ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
10
100
1k
10k
100k
1M
10M
100M
Fibre Channel Jitter Filter
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
dBc
Hz
N
OISE
P
OWER
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
6
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
159.375MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
159.375MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.75ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
Fibre Channel Jitter Filter
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
N
OISE
P
OWER
dBc
Hz
T
YPICAL
P
HASE
N
OISE
AT
156.25MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
156.25MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.58ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
10Gb Ethernet Jitter Filter
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
Raw Phase Noise Data
N
OISE
P
O
WER
dBc
Hz
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
7
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
212.5MH
Z
212.5MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.70ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
Fibre Channel Jitter Filter
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
dBc
Hz
N
OISE
P
O
WER
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
8
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
Q0:Q3
t
PD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
Q0:Q3
TEST_CLK
RMS P
HASE
J
ITTER
O
UTPUT
S
KEW
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V0.165V
P
ROPAGATION
D
ELAY
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
V
CC
,
V
CCA
, V
CCO
V
EE
nQ0:nQ3
nQ0:nQ3
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
tsk(o)
Qy
Qx
nQy
nQx
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
9
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843004 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distor tion.
Figures 2A and
2B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
10
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843004 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 3
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
ICS843004
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
Zo = 50 Ohm
U1
ICS843004
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
nQ
1
Q1
VC
C
O
Q0
nQ
0
MR
nPLL_S
EL
NC
VC
C
A
F_
S
E
L
0
VC
C
F_
S
E
L
1
XT
AL_O
U
T
XT
AL_I
N
VEE
T
EST
_C
LK
nXT
A
L_
SEL
VC
C
VEE
nQ
3
Q3
VC
C
O
Q2
nQ
2
R7
133
VCC
C1
27pF
RU1
1K
C8
0.1u
To Logic
Input
pins
VCCO=3.3V
C2
33pF
Set Logic
Input to
'1'
C7
0.1u
Zo = 50 Ohm
R5
133
C4
0.01u
Set Logic
Input to
'0'
To Logic
Input
pins
VCCA
X1
25MHz
C3
10uF
+
-
VCC
RD2
1K
VC
C
O
VCC=3.3V
C6
0.1u
R4
82.5
18pF
RU2
Not Install
+
-
VDD
R3
133
3.3V
VDD
R10
82.5
Zo = 50 Ohm
R9
133
VCCO
Logic Control Input Examples
R6
82.5
R2
10
R8
82.5
RD1
Not Install
Zo = 50 Ohm
VC
C
3.3V
C9
0.1u
L
AYOUT
G
UIDELINE
Figure 4 shows a schematic example of the ICS843004. An ex-
ample of LVEPCL termination is shown in this schematic. Addi-
tional LVPECL termination approaches are shown in the LVPECL
Termination Application Note. In this example, an 18pF parallel
F
IGURE
4. ICS843004 S
CHEMATIC
E
XAMPLE
resonant 26.5625MHz crystal is used. The C1=27pF and
C2=33pF are recommended for frequency accuracy. For differ-
ent board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy.
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
11
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843004.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843004 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 135mA = 467.8mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power
_MAX
(3.465V, with all outputs switching) = 467.8mW + 120mW = 587.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.588W * 65C/W = 123.2C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
6. T
HERMAL
R
ESISTANCE


JA
FOR
24-
PIN
TSSOP, F
ORCED
C
ONVECTION


JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
12
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
5. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
13
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843004 is: 2578
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP


JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
14
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
24 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
15
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM and F
EMTO
C
LOCKS
TM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
843004AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 18, 2004
16
Integrated
Circuit
Systems, Inc.
ICS843004
F
EMTO
C
LOCKS
TM LVCMOS/C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
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