Document Outline
- General Description
- Features
- Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Output Configuration & Frequency Range Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- AC Characteristics
- Parameter Measurement Information
- Application Information
- Power Supply Filtering Techniques
- Recommendations for Unused Input & Output Pins
- Crystal Input Interface
- Termination for 3.3V LVPECL Output
- Layout Guideline
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS843004-02 is a 4 output LVPECL
Synthesizer optimized to generate clock
frequencies for a variety of high performance
a p p l i c a t i o n s a n d i s a m e m b e r o f t h e
HiPerClocks
TM
family of high performance clock
solutions from ICS. This device can select its input reference
clock from either a crystal input or a single-ended clock signal
and can be configured to generate a number of different output
frequencies via the 3 frequency select pins (F_SEL2:0). The
ICS843004-02 uses ICS' 3rd generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase
jitter. This ensures that it will easily meet clocking requirements
for high-speed communication protocols such as 10 and 12
Gigabit Ethernet, 10 Gigbit Fibre Channel, and SONET. This
device is also suitable for next generation serial I/O
technologies like serial ATA and SCSI and is conveniently
packaged in a small 24-pin TSSOP package.
F
EATURES
Four 3.3V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Crystal input range: 14MHz - 37.78MHz
VCO Range: 560MHz - 680MHz
Supports the following applications:
SONET, Ethernet, Serial ATA, SCSI and HDTV
RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.91ps (typical)
Offset
Noise Power
100Hz ............... -97.1 dBc/Hz
1kHz .............. -121.6 dBc/Hz
10kHz .............. -124.9 dBc/Hz
100kHz .............. -125.1 dBc/Hz
Full 3.3V supply mode
0C to 70C ambient operating temperature
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
0
1
0
1
Phase
Detector
VCO
18
24
32
(default)
40
N
1
2
3
4
(default)
8
M
OSC
3
ICS843004-02
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQ1
Q1
V
CC
o
Q0
nQ0
MR
nPLL_SEL
nc
nc
V
CCA
F_SEL0
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
nQ2
Q2
V
CCO
Q3
nQ3
F_SEL2
nXTAL_SEL
TEST_CLK
V
EE
XTAL_IN
XTAL_OUT
F_SEL1
24
23
22
21
20
19
18
17
16
15
14
13
B
LOCK
D
IAGRAM
nPLL_SEL
XTAL_IN
XTAL_OUT
TEST_CLK
nXTAL_SEL
MR
F_SEL0:2
Q0
nQ
0
Q1
nQ1
Q2
nQ2
Q3
nQ3
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F
UNCTION
T
ABLE
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
2
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
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843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
3
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
3. O
UTPUT
C
ONFIGURATION
AND
F
REQUENCY
R
ANGE
F
UNCTION
T
ABLE
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843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
70C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = 0C
TO
70C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = 0C
TO
70C
l
o
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843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
5
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = 0C
TO
70C
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
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4C. LVPECL DC C
HARACTERISTICS
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V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = 0C
TO
70C
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843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
P
ARAMETER
M
EASUREMENT
I
NFORMATION
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0:Q3
RMS P
HASE
J
ITTER
O
UTPUT
S
KEW
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V0.165V
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
V
CC
,
V
CCA
, V
CCO
V
EE
nQ0:nQ3
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
tsk(o)
Qy
Qx
nQy
nQx
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
7
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843004-02 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1k
resistor can be
tied from XTAL_IN to ground.
T
EST
CLK
INPUT
:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1k
resistor can be tied from the TEST_CLK to ground.
S
ELECT
P
INS
:
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
843004AG-02
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REV. A JULY 20, 2005
8
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843004-02 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
ICS843004-02
C1
27p
XTAL2
XTAL1
C2
33p
X1
18pF Parallel Crystal
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distor tion.
Figures 3A and
3B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
843004AG-02
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REV. A JULY 20, 2005
9
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
L
AYOUT
G
UIDELINE
Figure 4 shows an example of ICS843004-02 application
schematic. In this example, the device is operated at V
CC
=3.3V.
The decoupling capacitor should be located as close as
possible to the power pin. Both input options are shown. The
device can either be driven using a quartz crystal or a 3.3V
To Logic
Input
pins
VCC
RD2
1K
C3
0.1uF
R5
50
Ro ~ 7 Ohm
Q1
Driv er_LVCMOS
C2
33pF
VCC
RD1
Not Install
MR
F_SEL2
Zo = 50 Ohm
+
-
C3
10uF
RU1
1K
VCCO
X1
19.44MHz
To Logic
Input
pins
Zo = 50 Ohm
C1
0.1uF
VCCO
Set Logic
Input to
'1'
VDD
F_SEL1
F_SEL0
U4
843004-02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
nQ
1
Q1
V
CCO
Q0
nQ
0
MR
nP
LL_S
E
L
NC
NC
VC
C
A
F_
S
E
L
0
VC
C
F_
S
E
L
1
XT
AL
_
O
U
T
XT
AL
_
I
N
VE
E
TE
S
T_
C
L
K
nX
T
A
L_
S
E
L
F_
S
E
L
2
nQ
3
Q3
VC
C
O
Q2
nQ
2
(U1-3)
R7
50
+
-
C2
0.1uF
Logic Control Input Examples
Zo = 50 Ohm
Zo = 50 Ohm
R8
43
R2
10
R5
133
VCCO=3.3V
Optional
Y-Termination
nPLL_SEL
C4
0.01u
R4
82.5
R6
82.5
R6
50
VDD
C1
27pF
3.3V
VCCA
nXTAL_SEL
(U1-12)
VCC
Set Logic
Input to
'0'
R3
133
VCC
Zo = 50 Ohm
VCC=3.3V
18pF
RU2
Not Install
(U1-22)
LVCMOS signal. For the LVPECL output drivers, only two
termination examples are shown in this schematic. Additional
termination approaches are shown in the LVPECL Termination
Application Note.
F
IGURE
4. ICS843004-02 S
CHEMATIC
E
XAMPLE
843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
10
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
-
TO
-3.3V LVPECL
F
REQUENCY
S
YNTHESIZER
PRELIMINARY
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843004-02 is: 3467
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843004AG-02
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REV. A JULY 20, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
-
TO
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D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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843004AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
12
Integrated
Circuit
Systems, Inc.
ICS843004-02
C
RYSTAL
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TO
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F
REQUENCY
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YNTHESIZER
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T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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