Document Outline
- General Description
- Features
- Frequency Select Function Table
- Pin Assignment
- Block Diagram
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- LVPECL DC Characteristics
- Crystal Characteristics
- AC Characteristics
- Typical Phase Noise Plot @ 62.5MHz
- Typical Phase Noise Plot @ 125MHz
- Typical Phase Noise Plot @ 156.25MHz
- Parameter Measurement Information
- 3.3V Core/3.3V Output Load AC Test Circuit Diagram
- Output Skew Diagram
- RMS Phase Jitter Diagram
- Propagation Delay Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Output Rise/Fall Time Diagram
- Application Information
- Power Supply Filtering Techniques
- Termination for 3.3V LVPECL Output
- Crystal Input Interface
- Layout Guideline
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
1
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS843004-01 is a 4 output LVPECL
synthesizer optimized to generate Ethernet
reference clock frequencies and is a member of
the HiPerClocks
TM
family of high performance clock
solutions from ICS. Using a 25MHz 18pF parallel
resonant crystal, the following frequencies can be generated
based on the settings of 2 frequency select pins (F_SEL[1:0]):
156.25MHz, 125MHz, 62.5MHz. The ICS843004-01 uses
ICS' 3
rd
generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS843004-01 is packaged
in a small 24-pin TSSOP package.
F
EATURES
Four 3.3V LVPECL outputs
Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
Supports the following output frequencies:
156.25MHz, 125MHz and 62.5MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.57ps (typical)
RMS phase noise at 156.25MHz (typical)
Phase noise:
Offset
Noise Power
100Hz ............... -95.5 dBc/Hz
1KHz ................ -118 dBc/Hz
10KHz ................ -126 dBc/Hz
100KHz .............. -126.6 dBc/Hz
Full 3.3V supply mode
-30C to 85C ambient operating temperature
HiPerClockSTM
ICS
P
IN
A
SSIGNMENT
1
1
0
1
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
OSC
M = 25 (fixed)
F_SEL[1:0]
0 0 4
0 1 5
1 0 10
1 1
not used
2
ICS843004-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQ1
Q1
V
CC
o
Q0
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MR
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CCA
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CC
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12
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CCO
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CC
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EE
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XTAL_OUT
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Pulldown
Pulldown
25MHz
Pulldown
Pulldown
Pulldown
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
2
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
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IN
C
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843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
3
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = -30C
TO
85C
T
ABLE
3B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = -30C
TO
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BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance,
JA
70C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = -30C
TO
85C
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C
.
V
2
-
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
4
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, TA = -30C
TO
85C
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
r
e
t
e
m
a
r
a
P
s
n
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843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
5
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.63ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
125MH
Z
T
YPICAL
P
HASE
N
OISE
AT
62.5MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.81ps
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
OWER
dBc
Hz
Raw Phase Noise Data
100
1k
10k
100k
1M
10M
100M
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
10Gb Ethernet Filter
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
10Gb Ethernet Filter
Raw Phase Noise Data
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
156.25MH
Z
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.57ps
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
OWER
dBc
Hz
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
Raw Phase Noise Data
10Gb Ethernet Filter
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
7
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
t
PW
t
PERIOD
t
PW
t
PERIOD
odc =
x 100%
Q0:Q3
RMS P
HASE
J
ITTER
O
UTPUT
S
KEW
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
2V
-1.3V0.165V
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
V
CC
,
V
CCA
, V
CCO
V
EE
nQ0:nQ3
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
tsk(o)
Qy
Qx
nQy
nQx
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
8
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843004-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
CCA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
CCA
10
F
.01
F
3.3V
.01
F
V
CC
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
2)) 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
designed to drive 50
transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distor tion.
Figures 2A and
2B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
9
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS843004-01 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values shown in
Figure 3
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 25MHz 18pF parallel reso-
nant crystal and were chosen to minimize the ppm error.
ICS843004-01
C1
33p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN
VCC=3.3V
VDD
VC
C
Zo = 50 Ohm
+
-
18pF
VC
C
O
R5
133
RD1
Not Install
To Logic
Input
pins
VCC
Zo = 50 Ohm
RU2
Not Install
3.3V
R9
133
U1
ICS843004-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
nQ
1
Q1
VC
C
O
Q0
nQ
0
MR
nP
LL_SEL
NC
VC
C
A
F
_
SEL0
VC
C
F
_
SEL1
XT
AL_OU
T
XT
AL_I
N
VE
E
T
E
ST
_C
LK
nXT
A
L_SE
L
VC
C
VE
E
nQ
3
Q3
VC
C
O
Q2
nQ
2
VCC
C3
10uF
+
-
R3
133
C7
0.1u
X1
25MHz
Zo = 50 Ohm
R7
133
3.3V
VDD
R6
82.5
VCCA
C4
0.01u
C8
0.1u
VCCO=3.3V
Logic Control Input Examples
C6
0.1u
C2
33pF
C9
0.1u
R2
10
RU1
1K
R4
82.5
Set Logic
Input to
'1'
C1
27pF
To Logic
Input
pins
R10
82.5
Zo = 50 Ohm
R8
82.5
Set Logic
Input to
'0'
VCCO
RD2
1K
L
AYOUT
G
UIDELINE
Figure 4 shows a schematic example of the ICS843004-01. An
example of LVEPCL termination is shown in this schematic. Ad-
ditional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18pF
F
IGURE
4. ICS843004-01 S
CHEMATIC
E
XAMPLE
parallel resonant 25MHz crystal is used. The C1=27pF and
C2=33pF are recommended for frequency accuracy. For differ-
ent board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy.
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
10
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843004-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843004-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 135mA = 467.8mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30mW = 120mW
Total Power
_MAX
(3.465V, with all outputs switching) = 467.8mW + 120mW = 587.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is:
85C + 0.588W * 65C/W = 123.2C. This is below the limit of 125C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
T
ABLE
6. T
HERMAL
R
ESISTANCE
JA
FOR
24-
PIN
TSSOP, F
ORCED
C
ONVECTION
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 5.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
0.9V
(V
CCO_MAX
- V
OH_MAX
) = 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
(V
CCO_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC_MAX
- V
OH_MAX
))/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC_MAX
- V
OL_MAX
))/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
F
IGURE
5. LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
12
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS843004-01 is: 3183
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
65C/W
62C/W
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
13
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
24 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
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843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
14
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
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The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
843004AG-01
www.icst.com/products/hiperclocks.html
REV. B MAY 6, 2005
15
Integrated
Circuit
Systems, Inc.
ICS843004-01
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
E
E
H
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